TB62718AFG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62718AFG
Controller and Driver for Full-color LED Modules and Panels
The TB62718AFG is an LED driver which is suitable for driving full-color LED modules. This device has built-in 8 bit PWM grayscale and an output current adjustment functions. It can turn on to 16 LEDs. This device has a heat sink fitting side on the surface of the package. Then, a heat sink will dissipate heat generated in the device. In addition, this device incorporates built-in TSD (thermal Shutdown) and output-open detection functions to protect the device.
Features
• Output current capability and number of outputs: 90 mA × 16 outputs • Constant current range: 5 mA~75 mA
• Application output voltage: 0.7 V (output current 5 mA~90 mA) • Adjustment function
Weight: 0.26 g (typ.)
1. Standard current adjustment (8-bit serial data input)
This function supports standard current adjustment using an external resistance connected to the REXT pin. 2 high-order bits … Output current can be adjusted to any one of 4 levels in the range 25%~100%. 6 low-order bits … Output current can be adjusted to any one of 64 levels in the range 40%~100%. 2. Each dot adjustment (128-bit serial data input)
This function allows adjustment of the current value for each output (dot). … Output current can be adjusted to any one of 64 levels in the range 20%~100%. 3. All dot adjustment 1 (8-bit parallel data input)
This function allows adjustment of brightness for each LED module. 5 low-order bits … Output current can be adjusted to any one of 32 levels in the range 50%~100%.
4. All dot adjustment 2 (8-bit parallel data input)
This function allows changes to the frequency of the PWM clock and allows major brightness adjustment for the display. 3 high-order bits … PWM clock frequency can be adjusted to any one of 8 levels in the range 1/1~1/8. 5. 256-grayscale PWM function (8-bit parallel input)
This function controls the pulse width for each output, yielding 256 grayscales.
Maximum PWM clock frequency 10 MHz (for all temperature range), Minimum pulse width 2 ms • Accuracy of bits in constant-current output levels prior to adjustment ±6.0% max (for output current of 40 mA~80 mA) ±7.0% max (for output current of 20 mA~40 mA) ±12.0% max (for output current of 5 mA~20 mA)
• Protection functions
1. Thermal shutdown function (TSD)
This function monitors the rise in junction temperature.
Connect a pull-up resistor to the ALARM1 pin in order to monitor the temperature.
2. Output Pin Open Detection function
This function detect when an output pin is open.
Connect a pull-up resistor to the ALARM2 pin in order to monitor this.
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Toll Free: 800.984.5337
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Web: www.marktechopto.com | Email: info@marktechopto.com
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TB62718AFG
• For anode-common LEDs
• Input signal voltage level: CMOS level (Schmitt trigger input) • Power supply voltage range VDD = 4.5 V~5.5 V • Maximum output pin voltage: 26 V
• Serial and parallel data transfer rate: 20 MHz (max, cascade connection) • Operating temperature range Topr = −40°C~85°C • Package: HQFP64-P-1010-0.50. A Heat sink can be fitted.
Warnings
Short-circuiting an output pin to GND or to the power supply pin may destroy the device. Take care when wiring the output pins, the power supply pin and the GND pins (VSS, VSS2). Do not apply either positive or negative voltages to the heat sink on the surface of the IC. In addition, do not solder anything to the heat sink.
22005-04-20
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TB62718AFG Pin Assignment (top view) and Markings
Package type: HQFP64-P-1010-0.50
PI DATA 01 PI DATA 02 PI DATA 03 PI DATA 04 PI DATA 05 PI DATA 06 PI DATA 07 PI DATA 08 PI LATCH OUT 00 32PI CLK PI SEL 48 33DOE SI DATA SI CLK SI LATCH SI SEL PWMCLK BCEN DCEN RESET 49 VSS2 VDD VSS NC TB62718AFGOUT 01 OUT 02 OUT 03 OUT 04 OUT 05 OUT 06 OUT 07 VSS2 VSS2 OUT 08 OUT 09 OUT 10 OUT 11 OUT 12 OUT 13 LED TEST BLANK REXT VSS SO DATA TSENA TEST0 64 5WWKA**1 16PO DATA 00 PO DATA 01 PO DATA 02 PO DATA 03 PO DATA 04 PO DATA 05 PO DATA 06 PO DATA 07 ALARM1 ALARM2 OUT 15 TEST1 VSS VSS2 VDD NC 17OUT 14
Note:
Details of weekly code on lower surface:
From left,
1st character = rightmost digit of year 0 for 2000, 1 for 2001
2nd and 3rd characters = week of manufacture during year: maximum value = 52. 4th characters = manufacturing factory (‘K’ means the Kita Kyushu factory.) 5th to 7th characters = lot number within week
1st lot is A11, 2nd lot is A1 and 3rd lot is A. 4th lot is B11, 5th lot is B1 and 6th lot is B. 64th lot is Z11, 65th lot is Z1 and 66th lot is Z.
The four characters of ‘I’, ‘M’, ‘O’ and ‘W’ are not used.
Indicates device name on the upper surface of the package. Indicates weekly code on the lower surface of the package.
32005-04-20
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TB62718AFG Constant Current Adjustment Range (graph)
This graph shows how current may be adjusted to a fraction of its full-scale value.
Note 1: In each case, the value input to each DAC is the value output from the previous DAC.
Reference: Current adjustment functions
DAC1 to DAC3 are the current adjustment functions for all outputs.
The adjustment width of DAC1 is large and approximate (1 LSB∼ − 25%).
The adjustment width of DAC2 is the smallest and has a large error (1 LSB∼ − 0.9%).
The adjustment width of DAC3 is small. DAC3 is a high-performance DAC with a small error
(1 LSB∼ − 1.61%).
Therefore,
It is recommended that DAC1 and DAC2 be used for adjusting the REXT resistance. It is recommended that DAC3 be used for adjusting brightness between module. (after it was set and it had DAC4 adjusted to the dot.)
The beginning is set in about 75% of the middle value, after that, it is effective to use ±25% of set width. DAC4 is the current adjustment function for all outputs.
The adjustment width of DAC4 is small. But it is a high-performance DAC with a small error (1 LSB∼ − 1.27%).
And also, DAC4 has a very wide setting range.
Therefore, DAC4 can be used to adjust the brightness of LEDs without a rank classification.
This method allows brightness to be adjusted with a degree of accuracy of 1.27% of full scale.
Note 2: Assuming precise linear correlation between output current and LED brightness
52005-04-20
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TB62718AFG Equivalent Input and Output Circuits (resistance values are typical values.)
Input pins with pull-up resistor
TSENA, BLANK, BC/DCEN
Input pins with pull-down resistor.
SI/PI LATCH, PI DATA 00~PI DATA 07, LED TEST
VDD R (UP) = 300 kΩVDD IN IN1 kΩ GND1 kΩ GND
R (DOWN) = 300 kΩ Input terminals (A) SI DATA, SI CLK, PI CLK, PWMCLK (B) RESET, DOE, PI SEL, SI SEL
VDD Output terminals PO DATA 00~PO DATA 07, SO DATA VDDIN Rin 100 Ω GND OUT GND (A) Rin = 250 Ω
(B) Rin = 1 kΩ
Protection circuit monitor terminals
ALARM1 & ALARM2 Parasitic diode VSS
Constant-current output terminals
OUT 00~OUT 15Parasitic diode VSS2
62005-04-20
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TB62718AFG Explanation of Pin Functions Table
No. Name I/O 4, 45 35, 14 VSS NC P ⎯ ⎯ Function Explanation Logic ground pins. Be sure to use all. ⎯ Unused This pin is used to reset the IC’s built-in temperature monitoring circuit (TSD). Pull- Rising edge of input signal re-enables outputs which had been forced to OFF. 63 TSENA I up The latched data as the setting is not reset. Either in case of H- or L-level of this terminals can be operated TSD circuit. 15, 24, 25, 34 13, 36 16~23, 26~33 VSS2 P ⎯ VDD OUT 00~ OUT 15 P O ⎯ ⎯ Ground pin for output. Be sure to use all. Logic power supply input pins. Be sure to use all. LED drive output pins. Connect to cathode of LED. Serial data input pin. Used for input of standard current adjustment data and dot adjustment data Serial data transfer clock input pin. Data is transferred positive edge. 50 SI DATA I ⎯ 51 SI CLK I ⎯ Pull- 52 SI LATCH I Serial data latch signal input pin. Data is held on positive edge. down 53 SI SEL I ⎯ 62 SO DATA O ⎯ 37~44 PI DATA 00~ PI DATA 07 I Serial data selection pin. Either standard current adjustment data or dot adjustment data may be selected. Serial data output pin. The output data type is selected using SI SEL. Pull- Input pins for parallel data. Inputs for all output adjustment data and PWM data down Input pin for parallel data transfer clock. Data is transferred on positive edge. 46 PI CLK I ⎯ Pull- 47 PI LATCH I Input pin for parallel data latch signal. Data is held on rising positive edge. down 48 PI SEL I ⎯ 5~12 PO DATA 00~ PO DATA 07 O ⎯ Parallel data selection pin. Either all output adjustment data or PWM data may be selected. Output pin for parallel data. The output data type is selected using PISEL. Control pin for parallel data output PODATA. PIDATA is out on input of an H-level signal. PIDATA is set to High-impedance by input of an L-level signal. 49 DOE I ⎯ Pull- PWM circuit control signal input pin. Output is turn OFF by input of an H-level signal. PWM 59 BLANK I up output is initiated by input of an L-level signal accordingly to the input data. 54 PWMCLK I ⎯ Standard clock input pin for PWM circuit. One clock cycle is equivalent to the minimum pulse width of the PWM output. Selection signal input pin for all output adjustment functions. All output adjustment is fixed Pull- 55 BCEN I to 100% when this signal is Low. All bit adjustments become effective when it is High. up It isn’t influent anything to all output adjustment by PWMCLK. Pull- Selection signal input pin for dot adjustment function. Dot adjustment value is fixed to 56 DCEN I up 100% when this signal is Low. Dot adjustment becomes effective when it is High. 57 ⎯ RESET I Reset signal input pin. Setting and registered data are reset when it is Low. A reset also releases TSD. Connection confirmation signal input pin for an LED. When this signal is High, all outputs Pull- 58 LED TEST I are ON. down This signal should normally be kept Low. 60 REXT P ⎯ 2 ALARM1 O ⎯ 3 ALARM2 O ⎯ 1, 64 TEST 0, TEST 1 I ⎯ Connection pin of resistor for setting for the current. Open-drain monitor pin for TSD circuit. When the TSD circuit detects an abnormal temperature, this signal is turned ON. IO monitor the TSD circuit connect this pin to a pull-up resistor. ALARM1 is independent of the RESET signal. Open-drain monitor pin for output-open detection circuit. When an open output is detected, this signal is turned ON. Pins for the device testing. Connect all these pins to ground. Pin attributes P: power supply/ground/other, I: input pin, O: output pin
Note 3: It is recommended that pins with pull-up or pull-down resistors not be left open.
Ambient noise may cause malfunction of the device.
72005-04-20
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TB62718AFG Absolute Maximum Ratings (Topr = 25°C unless otherwise specified)
Characteristics Symbol Rating Unit Supply voltage
Constant-current output voltage Output current Logic output voltage Logic input voltage Total VSS2 current Power dissipation Saturation heat
resistance of package
When device mounted on PCB
(Note 5)(Note 6)
VDD VO
−0.3~7 V −0.3~26 V IOUT 90 mA/bitVOUT VIN
−0.3~ VDD + 0.3 −0.3~VDD + 0.3
V V
IVSS2 1.44 A Pd (Note 4) θ (j-a)
1.19 5.0 102
When device mounted on PCB of any sizeWhen device mounted on PCB
(Note 6)
W
When device mounted on PCB of any size
°C/W θ (j-c) 25 Topr Tstg
−40~85 °C −55~150 °C Operating temperature Storage temperature
Note 4: If the operating temperature exceeds 25°C, derate the power dissipation rating by 0.95 mW/°C. Note 5: All four VSS2 pins must be connected. If not, device characteristics cannot be guaranteed. Note 6: When device mounted on PCB with dimensions 100 mm × 100 mm × 1.6 mm
Recommended Operating Conditions
(VDD = 4.5 V~5.5 V, Topr = −40°C~85°C unless otherwise specified)
Characteristics Symbol Conditions & Pins Min Typ. MaxUnit
Supply voltage High-level input voltage
VDD VIH VIL IOH IOL IOUT VOUT VOH Topr
⎯
4.5 5.0 5.5 V 0.7
VDD VSS ⎯ ⎯
⎯
PI DATA, PI CLK, PI SEL, PI LATCH, SI DATA, SI CLK, SI SEL, SI LATCH, PWM CLK
BLANK, LED TEST, TSENA, DOE, DCEN, BCEN
PO DATA 00~PO DATA 07, SO DATAVDD = 4.5 V, ALARM1, ALARM2 OUT 00~OUT 15 OUT 00~OUT 15 OFF ALARM1, ALARM2 OFF
⎯
VDD0.3 VDD
V
Low-level input voltage High-level output current Low-level output current Constant-current output Output voltage Operating temperature
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
V
−1 mA1 mA80 mA/bit26 V 5 V 85 °C 5 ⎯ ⎯ −40
82005-04-20
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TB62718AFG Recommended Operating Conditions (continue)
(VDD = 4.5 V~5.5 V, Topr = −40°C~85°C unless otherwise specified)
Characteristics Symbol fPWM Condition & Terminals Ratio of High-level: Low level = 50%, PWM CLK Min ⎯ ⎯ ⎯ ⎯ ⎯ Typ. ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Max10 15 10 15 10 ⎯ ⎯ ⎯ UnitfPI1 PI CLK, Clock frequency fPI2 PI CLK, connected in cascade MHzfSI1 SI CLK fSI2 twH/twL twltH/twltL twrstH/twrstLtwblkH/twblkLtwledH/twledLSI CLK, connected in cascade PWM CLK PI CLK, SI CLK PI LATCH, SI LATCH 30 30 50 Minimum pulse width ns RESET 50 ⎯ ⎯ BLANK 400 ⎯ ⎯ LED TEST PI DATA → PI CLK PI LATCH → PI CLK 400 10 10 10 10 50 5 5 5 5 50 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Set-up time tsetup SI DATA → SI CLK SI LATCH → SI CLK SI LATCH → SI CEL PI DATA → PI CLK PI LATCH → PI CLK ns Hold time thold SI DATA → SI CLK SI LATCH → SI CLK SI LATCH → SI CEL ns
92005-04-20
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TB62718AFG Electrical Characteristics 1
Parameter
High-level output voltage
(VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, typ: VDD = 5.0 V, Topr = 25°C)
Symbol VOH
Test conditions & Terminals IOH = −1.0 mA,
PO DATA 00~PO DATA 07, SO DATA
Min VDD −0.4 ⎯ ⎯ ⎯ ⎯
Typ. ⎯
MaxUnit
⎯ V Low-level output voltage
IOL = 1.0 mA, PO DATA 00~PO DATA 07, SO DATAVOL
IOL = 1.0 mA, ALARM1, ALARM2 VOUT = VDD or VSS,
PO DATA 00~PO DATA 07 All pins without pull-up/pull-down resistors
PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK
PI CLK = SI CLK = 20 MHz PWMCLK = L, BLANK = H Settings: *1
PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *5a
PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK
PI CLK = SI CLK = PWMCLK = 20 MHzSettings: *5a
PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *6a
PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK
PI CLK = SI CLK = PWMCLK = 20 MHzSettings: *6a
⎯ 0.4 ⎯ 0.3 ±0.5 ⎯
±5 ±1
V
Tri-state output leakage current Input current
IOZ II
µA µA
IDD1
⎯ 20 30 IDD2
⎯ 75 105
Supply current
IDD3
⎯ 80 115
mA
IDD4
⎯ 90 140
IDD5
⎯ 95 150
Electrical Characteristic Settings
(OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 kΩ unless otherwise specified)
No. DAC Settings ∗1
Surface Brightness
Adjustment (DAC3) Constant Output Current
(typ.) IOUT = 0 mA IOUT = 7.10 mA IOUT = 10.0 mA
Outputs all OFF, VOUT = 26 V, DAC1, 2, 4 = MSB, BLANK =H
∗2 DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L ∗3a DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L ∗4a DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5a DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6a DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L ∗7 DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L ∗3b DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L ∗4b DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5b DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6b DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L
DAC3 = 31
IOUT = 19.9 mA IOUT = 40.1 mA IOUT = 60.2 mA IOUT = 71.0 mA IOUT = 5.0 mA IOUT = 10.0 mA IOUT = 20.0 mA IOUT = 30.1 mA
DAC3 = 00
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TB62718AFG Electrical Characteristics 2
(VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, typ: VDD = 5.0 V, Topr = 25°C)
Parameter Symbol Test Conditions Min Typ. MaxUnit
IOUT1 Settings *7 60.4 71.0 81.6IOUT2
Constant-current output
IOUT3 IOUT4 IOUT5 IOUT6
Constant-current output Depends on
temperature
Leakage current for constant-current output
%TOPR1 %TOPR2 IOLK ∆IOUT1
Settings *6a 51.2 60.2 69.2Settings *5a 34.1 40.1 46.1
V
Settings *4a 16.5 19.9 23.2Settings *3a 7.8 10.0 12.2Settings *2 4.54 7.1 9.65Settings *6a, VOUT = 1.0 V, Topr is varied in the range −40°C~85°C. Settings *4a, VOUT = 1.0 V, Topr is varied in the range −40°C~85°C. Settings *1, VOUT = 26 V Settings *6a, VOUT = 0.7 V Settings *5a, VOUT = 0.7 V Settings *4a, VOUT = 0.7 V Settings *3a, VOUT = 0.7 V
Settings is changed from *6a to *6b. Settings is changed from *5a to *5b. Settings is changed from *4a to *4b. Settings is changed from *3a to *3b. Settings *6a, VOUT is varied in the range 0.7 V~3 V.
Settings *4a, VOUT is varied in the range 0.7 V~3 V.
Settings *6a, VDD is varied in the range 4.5 V~5.5 V.
⎯ ⎯
⎯ ⎯
±50 ±25
±80
µA/°C
±50
⎯ 0.05 0.1 µA ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
±2.5 ±3.5 ±5.5 ±7 ±1 ±1.5 ±3.5 ±6 ±5 ±3 ±1
±6 ±6 ±7 ±12±3 ±3 ±5 ±12±8
Constant current accuracy between bits
∆IOUT2 ∆IOUT3 ∆IOUT4
%
Dot adjustment deviation between bits
(when DAC3 data were changed from MSB to LSB.)
%IOUT1 %IOUT2 %IOUT3 %IOUT4
%
Constant-current output depends on output voltage
Constant-current output depends on supply voltage
TSD detection temperature Output-open detection voltage Pull-up/down resistor
%VOUT
%
±6
±2 % %VDD Tsd1 Tsd2 VARL Rup/Rdw
120 140 160140 160 180⎯
°C
ALARM2
⎯
0.04 VDD
⎯ V 150 300 600kΩ
Electrical Characteristic Settings
(OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 kΩ unless otherwise specified)
No. DAC Settings ∗1 OUT00~15 OFF, VOUT = 26 V, DAC1~4 = MSB, BLANK = H ∗2 DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L ∗3a DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L ∗4a DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5a DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6a DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L ∗7 DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L ∗3b DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L ∗4b DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L ∗5b DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L ∗6b DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L
All Dot Adjustment
(DAC3) Constant Output Current
(typ.) IOUT = 0 mA IOUT = 7.10 mA IOUT = 10.0 mA
DAC3 = 31
IOUT = 19.9 mA IOUT = 40.1 mA IOUT = 60.2 mA IOUT = 71.0 mA IOUT = 5.0 mA IOUT = 10.0 mA IOUT = 20.0 mA IOUT = 30.1 mA
DAC3 = 00
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TB62718AFG Switching Characteristics
(VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, CL = 50 pF unless otherwise specified,
typ: VDD = 5.0 V, Topr = 25°C, CL = 50 pF)
Parameter Symbol Test Conditions Min Typ. MaxUnitTri-state output enable propagation delay Tri-state output disable propagation delay Rise time → PO DATA0~ PO DATA 7 tpZH/ZL DOE 8 8 10 16 16 17 30 30 30 ns ns µs tpHZ/LZ DOE → PO DATA0~ PO DATA 7 tr OUT00~ OUT 15 ALARM1, ALARM2 OUT00~ OUT 15 ALARM1, ALARM2 0.2 0.4 0.8 ns 20 ns 2 4 8 60 120 70 12020014040 70 Fall time tf tpHL BLANK → OUT00~ OUT 15 tpLH PWM CLK → OUT00~ OUT 15 tpHL PWM CLK → OUT00~ OUT 15 30 70 40 Propagation delay tpLH 60 110 190LED TEST → OUT00~ OUT 15 tpHL 30 60 130ns tpHL 30 60 130RESET → OUT00~ OUT 15 PI CLK → PO DATA0~ PO DATA 7 tpd PI SEL → PO DATA0~ PO DATA 7 SI SEL → SO DATA SO DATA SI SEL → 20 20 30 30 70 70 10 18 40 10 20 40
122005-04-20
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TB62718AFG Explanation of Operation and Truth Tables
Serial data transfer: standard current adjustment using DAC1 and DAC2 (data register SI REG [7:0])
Process SI DATA SI CLK 1 H or L 2 (×8) L (×1) H No changeL H H or L SI LATCHSI SELSO DATAOperation and Function Selects standard current adjustment (8 bits, 2 bits and 6 bits) for input data when SI SEL is high. Data is transferred to SI REG [1] on 8th positive edge of SI CLK input. Holds the data transferred to SI REG [1] on positive edge of SI LATCH. Set is reflected on standard current adjustment from the moment when it is held.
Serial data transfer timing
(standard current adjustment, SI SEL = H, single device)
RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = LSODATA is synchronized with 8th clock cycle after reset, and the first data is output.
Data held on positive edge of SI LATCH after the data transfer by single device (after 8 clock cycles)Indicates undefined logic state after reset and before input.
Serial data transfer timing
(standard current adjustment, SI SEL = H, two devices connected in cascade)
RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) LData reset by RESET = Indicates undefined logic state after reset and before input. SODATA is synchronized with 8th clock cycle after reset, and the first data is output.
Data held on positive edge of SI LATCH after the data transfer by two devices (after 16 clock cycles)
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TB62718AFG Serial data transfer: dot adjustment DAC4. (data register SI REG2 [127:0])
Process SI DATA SI CLK 1 H or L 2 (×128) L (×1) L No changeHolds the data transferred to SI REG2 on positive edge of SILATCH. Set is reflected on dot adjustment from the moment when it is held. L L H or L Selects dot adjustment (128 bits) for input data. Data is transferred to SI REG2 on 128th positive edge of SI CLK.SI LATCHSI SELSO DATAOperation and Function
Serial data transfer timing
(dot adjustment, SI SEL = L, single device)
RESET SI SEL SI DATA SI CLK There pairs of bits are Don’t care. Dot adjustment data for OUT 15 (1st device). SI LATCH SO DATA (1st device) Dot adjustment data for OUT 00 (1st device). Data held on positive edge of SI LATCH after data transfer by single device (after 128 clock cycles) Data reset by RESET = LIndicates undefined logic state after reset and before input.
SODATA is synchronized with 128th clock cycle after reset, and the first data is output.
Serial data transfer timing
(dot adjustment, SI SEL = L, two devices connected in cascade)
RESET SI SEL SI DATA SI CLK There pairs of bits are Don’t care. Dot adjustment data for OUT 15 (1st device). SI LATCH SO DATA (1st device) Dot adjustment data for OUT 00 (1st device). Dot adjustment data for OUT 15 (2nd device). Dot adjustment data for OUT 00 (2nd device). Data reset by RESET = LIndicates undefined logic state after reset and before input. SODATA is synchronized with 128th clock cycle after reset, and the first data is output. Data held on positive edge of SI LATCH after data transfer by two devices (after 256 clock cycles)
142005-04-20
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TB62718AFG DAC1: Standard current adjustment settings for DAC1 (SI REG1 [7:6])
SEL RESET SI SI REG (7:6) SI REG (5:0) Current Rate Operation and Function Notes 100% H H HH XXXXXX (1.0) 75% H H HL XXXXXX (0.75) 50% H H LH XXXXXX (0.5) 25% H H LL XXXXXX (0.25) 25% X LL LLLLLL (0.25) 100% of base current setting as determined by REXT (Ω) When SI SEL = H, 2 bits on 75% of base current setting as determined by REXT MSB sides are (Ω) corresponding to set of standard 50% of base current setting as determined by REXT current (Ω) adjustment 25% of base current setting as determined by REXT DAC1. The output (Ω) current can be Initial state after input of reset signal: 25% of base set to one of 4 levels. current setting as determined by REXT (Ω) (as described above)
DAC2: Standard current adjustment settings for DAC2 (SI REG1 [5:0]) SEL RESET SI SI REG (7:6) SI REG (5:0) Current Rate Operation and Function 100% of base current value as set using DAC1 base current adjustment When SI SEL = H, 6 bits on Any one or 64 levels in the range 40%~100% of the MSB sides are current can be set. (1 LSB = 0.95%) corresponding to 6-bit DAC performance set of standard 1LSB variation: ±0.95% current Non linearity error: ±1/2LSB adjustment Differential non linearity error: ±3/4LSB DAC2. The output current can be 40% of base current value as set using DAC1 base set to one of 64 current adjustment levels. Initial state after input of reset signal: 40% of base current value set as described above Notes 100% H H XX XXXXXX (1.0) HHHHHL↑ H H XX ↓ LLLLLH (0.9905)↑ 1LSB =±0.95%(±0.0095) ↓ (0.4095)40% H H XX LLLLLL (0.4) 40% X LL LLLLLL (0.4)
DAC4: Set details of dot adjustment DAC4 (SI REG2 [127:0]) SEL DCEN RESET SI About 8 bits Unit of SI REG2 [127:0] Current Rate Operation and Function Output current is 100% of base current value as set using DAC1 and DAC2 base current adjustment and DAC3 surface brightness adjustment Any one of 64 levels in the range 20%~100% of the current can be set. (1LSB∼ − 1.27%) 6-bit DAC performance 1LSB variation: ±1.269% Non linearity error: ±1/2LSB Differential non linearity error: ±1/2LSB Notes When SI SEL = L 8 bits out of 128 bits are corresponding to set of each output, and the 6 bits on MSB sides of 8 bits are data on dot adjustment. The output current can be set to one of 64 levels. 100% H L H XXHHHHHH (1.0) XXHHHHHL ↑ H L H ↓ XXLLLLLH (0.9874)↑ 1LSB =±1.269%(±0.0126)↓ (20.0126)20% H L H XXLLLLLL (0.2) 20% X H XXLLLLLL (0.2) SI REG2 [7:0] → adjustment data for OUT 00. SI REG2 [15:8] 20% of base current value as set using → adjustment data for DAC3 surface brightness adjustment OUT 01. Initial state after input of reset signal: 20% SI REG2 [127:120] → adjustment data for of base current value set as described OUT 15. above Output current is 100% of base current value set as described above. Data input is still enabled if DCEN = L. If DCEN = H, adjustment is performed at the same time. 100% H X L XXHHHHHH (1.0)
152005-04-20
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TB62718AFG Polarity of serial input data for standard current adjustment (SI REG1 [7:0]) and dot adjustment (SI REG2 [127:0])
Serial data transfer timing
(SI SEL = H, input of standard current adjustment data for DAC1 and DAC2)
Standard current adjustment data (6 bits)SI DATA Standard current adjustment data (2 bits) SO DATAD-F/F D-F/F D-F/F D-F/FD-F/FD-F/FD-F/FD-F/FSI REG1 (7)SI REG1 (0) MSBLSB D-LAT D-LAT D-LATD-LATD-LATD-LATD-LATD-LATSI LATCH
Serial data transfer timing
(SI SEL = L, input of dot adjustment data for DAC4)
Not usedDot adjustment data (6 bits) SI DATA SI REG2 (0) LSB SI LATCH DAC4 (6-bit DAC) DAC4 (6-bit DAC) × × SI REG2 (7)Dot adjustment data (6 bits) Not used SI REG2 (120)SO DATA× × SI REG2 (127) MSB OUT 00 OUT 15
162005-04-20
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TB62718AFG Parallel data transfer: All dot adjustment DAC3. (data register PI REG1 [7:0])
Process PI DATA [7:0] PI CLK 1 H or L 2 (×1) L (×1) H No changeHolds the data transferred to PI REG1. Set is reflected on all dot adjustment from the moment when it is held. L H H or L PI LATCHPI SELPO DATA[7:0] Operation and Function Selects total dot adjustment (8-bit, 3-bit and 5-bit) for input data. Data is transferred to PI REG1 on 128th positive edge of PI CLK.
Parallel data transfer timing (all dot adjustment, PI SEL = H, single device)
RESET PI SEL PI DATA [7:0] PI CLK PI LATCH PO DATA [7:0] 000_00000 111_11111PO DATA is synchronized with 1st clock cycle after reset, and the first data is output.
Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) 111_11111Indicates undefined logic state after reset and before input.
Parallel data transfer timing
(all dot adjustment, PI SEL = H, two devices connected in cascade)
RESET PI SEL PI DATA [7:0] PI CLK PI LATCH PO DATA [7:0] (1st device) 000_00000 111_11111111_11111110_11110101_11101 Indicates undefined logic state after reset and before input. Data held on positive edge of PI LATCH after the data 110_11110transfer by two devices (2 clock cycles)PO DATA is synchronized with 2nd clock cycle after reset, and the second data is output. PO DATA is synchronized with 1st clock cycle after reset, and the first data is output.
172005-04-20
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TB62718AFG Parallel data transfer PMW display data (data register PI REG2 [127:0])
Process PI DATA PI CLK 1 H or L 2 (×16) L (×1) L No changeL L H or L PI LATCHPI SELPO DATAOperation and Function Selects for input data of PWM display data (8 bit × 16). Data is transferred to PI REG2 on 16th positive edge of PI CLK. Holds the data transferred to PI REG2. Set is reflected on PWM 256 grayscales from the next BLANK = L when it is held.
Parallel data transfer timing (PWM data PI SEL = L, single device)
RESET PWM data for OUT 15PI SEL PI DATA [7:0] PI CLK 01H 02H 0EH0FHPWM data for OUT 00 PI LATCH PO DATA [7:0] 00H 00H01HData held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) Indicates undefined logic state after reset and before input. PO DATA is synchronized with 16th clock cycle after reset, and is output.
Parallel data transfer timing (PWM data PI SEL = L, two devices connected in cascade)
RESET PI SEL PI DATA [7:0] PI CLK PWM data for OUT 15 (1st device) 00H 00HPWM data for OUT 00 (1st device) 01H02H0FH 10H 01H00H 01H 02H 0EH0FH10H01H02H0EH0FH 10H PI LATCH PO DATA [7:0] (1st device) Indicates undefined logic state after reset and before input. PO DATA is synchronized with 16th clock cycle after reset, and the first data is output.Data held on positive edge of PI LATCH after data transfer by two devices (32 clock cycles)
182005-04-20
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TB62718AFG Details all dot adjustment setting using PWMCLK division (PI REG1 [7:5])
SEL BCEN RESET PI PI REG1 [7:5] PWMCLK Divisor Operation and Function The period of PWMCLK is set to equal the change in the PWM pulse width data. 1LSB. Notes PWM CLK = H H H LLL 8/8 PWMCLK(Hz) When PI SEL = H is selected, 3 Variable does the frequency of LLH bits on MSB sides are PWMCLK to 1/8 of the minimal. It corresponding to set of standard ↑ 7/8 PWMCLKis set in 8 levels. current adjustment by PWM to H H H 6-bit DAC performance frequency dividing. 2/8 PWMCLKMaximum input: PWMCLK = 20 ↓ PI REG [7:5] varies the pulse MHz HHL width of PWM data PWMCLK = The period of PWMCLK is set to corresponding to 1 LSB for eight levels and adjusts brightness. H H H HHH 1/8 PWMCLKone-eighth the change in the This setting values affects pulse (Hz) PWM pulse width data. 1 LSB. widths on all outputs. PWMCLK = The period of PWMCLK is set to X H LLL 8/8 PWMCLKequal the change in the PWM (Hz) pulse width data. 1 LSB. BCEN signal does not affect H H L XXX Unchanged PWMCLK frequency dividing. Data input is still enabled if BCEN = L. Output current level reflects input settings.
DAC3: Details of all dot adjustment setting for DAC3 (PI REG2 [4:0]) SEL RESET PI PI REG1 [4:0] BCEN Current Rate Operation and Function 100% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment Any one of 32 levels in the range 50%~100% of the current can be set. (1 LSB = 1.61%) 5-bit DAC performance 1LSB variation: ±1.61% Non linearity error: ±1/2LSB Differential non linearity error: ±1/2LSB (No guarantee for monotonicity) 50% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment Initial state after input of reset signal: 100% of base current value set as described above Initial state after input of DCEN signal: 100% of base current value set as described above Data input is still enabled if BCEN = L. If BCEN = H, adjustment is performed at the same time. Notes 100% H H HHHHH H (1.0) HHHHL ↑ H H ↓ LLLLH (0.9839)↑ 1LSB = ±1.61%(±0.0161) ↓ (0.5161)H When PI SEL = H is selected, 5 bits on LSB side are corresponding to set of surface brightness adjustment. The output current can be set to one of 32 levels. 50% H H LLLLL H (0.5) 100% X HHHHH H (1.0) 100% H X HHHHH L (1.0)
192005-04-20
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TB62718AFG Detailed PWM 256 grayscales setting (PI REG2 [127:0], 16 × 8 bits)
SEL of PI REG2 RESET PI 1 word (8 bits) Output Pulse Rate Operation and Function Output pulse width is at its maximum value when input data is FF. Notes When PI SEL = L, The PWM grayscale controls the output pulse width. 255/255 H L HHHHHHHH 100% HHHHHHHL ↑ H L ↓ LLLLLLLH ⎯ 0/255 H L LLLLLLLL 0% 0/255 X LLLLLLLL 0% 16 × 8-bit words are transferred in parallel. The input data can be used to 1 word is the PWM data of each output control the PWM pulse width pulse width is set in 256 step. and hence generate 256 PI REG2 [7:0] grayscales. → PWM data for OUT 00. PI REG2 [15:8] → PWM data for OUT 01. Outputs are OFF when the PI REG2 [127:120] input data is 00. → PWM data for OUT 15. Early condition after the reset Minimum output pulse width is signal input is set in 0/256 1/PWMCLK. (output off).
Polarity of serial input data for all dot adjustment
(PI REG [7:0]) and PWM 256 grayscales (PI REG2 [127:0]) Parallel data transfer timing
(PI SEL = H, selects data input for all dot adjustment for DAC3.)
PI REG1 [7] MSB
PI DATA [7] All dot adjustment by division by PWMCLK PO DATA [7]
All dot adjustment by DAC3 PI DATA [0] LSB PI REG1 [0] PI LATCH PO DATA [0]
(PI SEL = L, selects data input for PWM 256 grayscales.)
PI REG2 [7] MSB
PI DATA [7] PO REG2 [127]MSB
PO DATA [7] PWM pulse data PWM pulse dataPI DATA [0] LSB PI REG2 [0] PI LATCH PWM pulse generator circuitOUT 00 LSBPI REG2 [120]PO DATA [0] PWM pulse generator circuit OUT 15 202005-04-20
元器件交易网www.cecb2b.com⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 48 110000 0.857 16 10000 0.758 47 101111 0.848 15 01111 0.742 46 101110 0.838 14 01110 0.726 45 101101 0.829 13 01101 0.710 44 101100 0.819 12 01100 0.694 43 101011 0.820 11 01011 0.677 42 101010 0.800 10 01010 0.661 41 101001 0.791 9 01001 0.645 40 101000 0.781 8 01000 0.629 39 100111 0.771 7 00111 0.613 38 100110 0.762 6 00110 0.597 37 100101 0.752 5 00101 0.581 36 100100 0.743 4 00100 0.565 35 100011 0.733 3 00011 0.549 34 100010 0.724 2 00010 0.532 33 100001 0.714 1 00001 0.516 32 100000 0.705 0 00000 0.500 31 011111 0.695 ⎯ 30 011110 0.686 ⎯ 29 011101 0.676 ⎯ 28 011100 0.667 ⎯ 27 011011 0.657 ⎯ 26 011010 0.648 ⎯ 25 011001 0.638 ⎯ 24 011000 0.629 ⎯ 23 010111 0.619 ⎯ 22 010110 0.610 ⎯ 21 010101 0.600 ⎯ 20 010100 0.591 ⎯ 19 010011 0.581 ⎯ 18 010010 0.571 ⎯ 17 010001 0.562 ⎯ 16 010000 0.552 ⎯ 15 001111 0.543 ⎯ 14 001110 0.533 ⎯ 13 001101 0.524 ⎯ 12 001100 0.514 ⎯ 11 001011 0.505 ⎯ 10 001010 0.495 ⎯ 9 001001 0.486 ⎯ 8 001000 0.476 ⎯ 7 000111 0.467 ⎯ 6 000110 0.457 ⎯ 5 000101 0.448 ⎯ 4 000100 0.438 ⎯ 3 000011 0.429 ⎯ 2 000010 0.419 ⎯ 1 000001 0.410 ⎯ 0 **000000 **0.4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Note 7: **: Indicates post-reset initialization value ( RESET= L). Note 8: The formula for calculating resistance settings is as follows: This value is theory value. Actual current value contains error aREXT [kΩ] = (1.9 × current rate 1 × current rate 2 × current rate 3 / output current [mA]) × (1 + (7 × current rate 4 / 105)) × 121元器件交易网www.cecb2b.com
TB62718AFG Reference table: output current setting value (2)
Reference value for standard current adjustment under conditions:
REXT = 2.7 kΩ (fixed), all dot adjustment = MSB and dot adjustment = MSB
Unit: mA
DAC2
0 1 2 3 4 5 6 7 8 9 10
0
DAC1 119.017.926.935.8
12 13 149.1 9.3 9.518.3 18.6 18.927.4 27.9 28.436.5 37.2 37.9159.619.328.938.6
7.1 7.37.4 7.6 7.87.915.923.831.8
8.116.224.332.5
8.316.624.933.1
8.516.925.433.8
8.617.225.934.5
8.817.626.435.2
1 2 3
14.2 14.5 14.9 15.2 15.621.3 21.8 22.3 22.8 23.328.4 29.1 29.6 30.4 31.1
DAC2
16 17 18 19 200
DAC1 2110.721.332.042.6
2210.821.632.543.3
2311.022.033.044.0
2411.222.333.544.6
2511.322.734.045.3
2611.523.034.546.0
2711.723.335.046.7
28 29 3011.8 12.0 12.223.7 24.0 24.335.5 36.0 36.547.3 48.0 48.73112.324.737.049.4
9.8 10.0 10.1 10.3 10.519.6 19.9 20.3 20.6 21.029.4 29.9 30.4 30.9 31.439.2 39.9 40.6 41.2 41.91 2 3
DAC2
32 33 34 35 360
DAC1 3713.426.740.153.4
3813.527.040.654.1
3913.727.441.154.8
4013.927.741.655.4
4114.028.142.156.1
4214.228.442.656.8
4314.428.743.157.5
44 45 4614.5 14.7 14.929.1 29.4 29.843.6 44.1 44.658.1 58.8 59.54715.030.145.160.2
12.5 12.7 12.9 13.0 13.225.0 25.4 25.7 26.0 26.437.5 38.0 38.6 39.0 39.650.0 50.7 51.4 52.1 52.71 2 3
DAC2
48 49 50 51 520
DAC1 5316.132.148.264.2
5416.232.548.764.9
5516.432.849.265.6
5616.633.149.766.3
5716.733.550.266.9
5816.933.850.767.6
5917.134.151.268.3
60 61 6217.2 17.4 17.634.5 34.8 35.251.7 52.2 52.769.0 69.6 70.36317.835.553.271.0
15.2 15.4 15.6 15.7 15.930.4 30.8 31.1 31.4 31.845.6 46.1 46.7 47.2 47.760.9 61.5 62.2 62.9 63.61 2 3
222005-04-20
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TB62718AFG Temperature detection function (can be monitored via the ALARM1 pin.)
Perform two-stage temperature detection as described in the table below (TSD1/TSD2). Junction Temperature [°C] ALARM1 OUT 00~OUT 15 Function ⎯ −40~120 OFF Normal operation When the chip temperature reaches the specified range the 120~ ON Normal operation ALARM1 signal goes Low (TSD1), Other functions are not affected. When the chip temperature reaches the specified range the ALARM1 signal goes Low and all output pins are turned OFF (TSD2). 140~ ON OFF Outputs are re-enabled on the positive edge of TSENA or when the RESET signal goes Low. Neither of these causes the internal data to be reset. If RESET pin = L, all internal data is reset.
Output-open detection function (can be monitored via the ALARM2 pin.)
Reform output-open detection as described in the table below.
Output Voltage [V]
ALARM2 Function OFF ON
> = VDD × 0.04 < = VDD × 0.04
⎯
The output-open condition is detected when the ARARM2 pin signal is ON
and the specified voltage level is detected. (it is also detected when the output voltage falls to near GND for some reason)
Pulse cancellation circuit
(when monitored using output-open detection pin ARARM2.)
PWMCLK ALARM2 Input signal No input
Operating Always OFF
Function
The built-in pulse cancellation circuit is designed to prevent malfunction. However, if there is no input on PWMCLK, ALARM2 output will not be turned ON.
232005-04-20
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TB62718AFG Block Diagram of Protection Circuit
RESET Output-OFF condition is released and internal data is reset. LED TEST Output ON TSENA ALARM1 Release of output OFF on positive edge Constant- current output Output OFFTSD2 TSD1 ALARM2 Pulse cancel Output-open detection Continue one, open condition is detected. 16OUT00~OUT15
Protection circuit function
Operating chart (terminal for TESNA, ALARM1 and outputs OUT 00~OUT 15)
TSENA RESET Junction Temperature (unit: °C) TSD1 TSD2 < < Tj< 120°C 120Tj 140= = = Tj < < = 160°C = 180°C ALARM1 OUT 00 ~ OUT 15 Function X L ○ X H ○ X L ⎯ X H ⎯ ⎯ ⎯ ○ ○ ⎯ ⎯ ⎯ ⎯ OFF ON Device reset OFF ON Outputs operate normally. ON ON Device reset ON Normal operationALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. X L ⎯ ⎯ Even after a reset, if the junction ○ ON OFF temperature is high, outputs are turned OFF. ALARM1 goes Low, indicating a ○ ON OFF rise in temperature. Outputs operate normally. X H ⎯ ⎯ Note 9: The internal operation of the TSD circuit is independent of the TSENA and RESET pin voltage levels.
242005-04-20
元器件交易网www.cecb2b.comSI LATCH SI CLK ×8 ×8 ×8 SI SEL Selects input of standard current adjustment data. Selects input of each dot adjustment data. SO DATA
The data read with 1st time SO DATA outputs standard current SO DATA outputs each dot adjustment data. The data read wit
Note 10: Serial data input has no effect on the ON/OFF state of the outputs.
When the SI LATCH signal holds the serial data, the output current values and output pulse width are affected.
Parallel Data Input Timing Chart
Output OFF & data holdBLANK
Output ON & data transfer Output ON & dRESET
DOE
PWM data for OUT 15PI DATA 00~ PI DATA 07 for total dot adjustment PI CLK 1 Time PI LATCH 16 TimesPWM data for OUT 00Holds PWM data, output-ON data and total dot adjustSelects input of total dot adjustment PI SEL PO DATA 00~ PO DATA 07 Selects input of PWM data and output-ON data. Selects input ooutput-High-Impedance High-Impedance The data reaThe data read with 1st time PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output all bit adjustment data. PO DATA 00~POPWMOUT 00~ OUT 15 Output ON (output-OFF if PWM data = 0) OFF Starts output of PWMsynchronizing with ri
Note 11: The BLANK signal has not effect on parallel data input. The PWM pulse can be controlled using the BLANK signal. It is recommended that, on completion of data transfer, BLANK be set to High and outputs be turned OFF. 25元器件交易网www.cecb2b.comtBLANK (8) tBLANK (7) tBLANK (6) PWMCLK division
tBLANK (5) tBLANK (4) tBLANK (3) tBLANK (2) tBLANK (1) tBLANK (7) = (1/ (7/8PWMCLK) ) × 256 tBLANK (6) = (1/ (6/8PWMCLK) ) × 256 Minimum PWM control time tBLANK (8) = (1/ (8/8PWMCLK) )tBLANK (5) = (1/ (5/8PWMCLK) ) × 256 tBLANK (4) = (1/ (4/8PWMCLK) ) × 256 tBLANK (3) = (1/ (3/8PWMCLK) ) × 256 tBLANK (2) = (1/ (2/8PWMCLK) ) × 256
Maximum PWM control time tBLANK (1) = (1/ (1/8PWMCLK) OUT 00~OUT 15 PWM data = 00 H OUT 00~OUT 15 PWM data = 01 H PWMCLK8 OUT 00~OUT 15 PWM data = 80 H PWMCLK8 OUT 00~OUT 15 PWM data = FE H PWMCLK8
Output OFF because data is 00H though it can on. Because data is 01 H output is ON with 1/255 of tBLANK. Because data is 80 H output is ON with 128/255 of tBLANK. Because data is 80 H output is ON with 254/255 of tBLANK.
Note 12: PWM operation timing:
PWM pulse output on the output pins is initiated when BLANK goes Low. (there is simultaneous output on all 16 pins) Output pulse only once toward BLANK signal’s changing once in L from H. Hence, if PWM data is to be re-used, BLANK must be pulled Low again.
PWMCLK division:
As shown in the central part of the upper figure, the brightness of the LED module can be set to any one of eight levels withcurrent value, simply by dividing by PWMCLK.
For large-scale brightness adjustment, division by PWMCLK is recommended.
26元器件交易网www.cecb2b.com
TB62718AFG Logic Input and Output Timing Waveforms
1. PI CLK (SI CLK) vs. PI DATA [7:0] (SI DATA) PI CLK (SI CLK) vs. PO DATA [7:0] (SO DATA)
twH PI CLK (SI CLK)
twL 50% 50%50%PI DATA [7:0]
(SI DATA)
50% 50%tsetup PO DATA [7:0]
(SO DATA)
thold 50%50%tpd tpd
2. PI SEL (SI SEL) vs. PI CLK (SI CLK)
twH PI CLK (SI CLK)
twL 50% 50%50%PI DATA [7:0]
(SI DATA)
PI SEL (SI SEL)
tsetup thold 50%50%50%tsetup thold
272005-04-20
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TB62718AFG 3. PI LATCH (SI LATCH) vs. PI CLK (SI CLK)
twH PI CLK (SI CLK)
twL 50% 50%50%PI DATA [7:0]
(SI DATA)
(Internal flip-flop data)
tsetupPI LATCH (SI LATCH)
50%thold 50%50%twltH twltL
4. PI SEL (SI SEL) vs. PO DATA 00~PO DATA 07 (SO DATA)
PI SEL (SI SEL)
50% 50%PO DATA [7:0]
(SO DATA)
tpd 50%50%tpd
5. DOE vs. PO DATA 00~PO DATA 07
DOE
50%50%PO DATA [7:0]
tpzH/zLtpzH/zL
282005-04-20
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TB62718AFG Logic Input and Constant-current Output Timing Waveforms
1. BLANK vs. OUT 00~OUT 15 with PWMCLK
twblkL twblkH BLANK
50% 50%50%50%PWMCLK
Maximum delay time is 1 PWMCLK cycle. OUT 00~OUT 15 (current waveform)
Maximum delay time is 1 PMCLK cycle. 50%50% tpLH tpHL
2. RESET vs. OUT 00~OUT 15
BLANK
twrstLRESET
50%50%OUT [15:0]
(current waveform)
tpHL 50%
3. LED TEST vs. OUT 00~OUT 15
twledH LED TEST
50%tpLH 50%OUT 00~OUT 15 (current waveform)
50%tpHL 50%
292005-04-20
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TB62718AFG Package Dimensions
Weight: 0.26 g (typ.)
302005-04-20
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TB62718AFG
About solderability, following conditions were confirmed • Solderability
Use of Sn-63Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux
Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux
RESTRICTIONS ON PRODUCT USE
000707EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice.
312005-04-20
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