MC100ES8011

Document Number: MC100ES8011H

Rev 2, 09/2005

Low Voltage 1:2 Differential HSTL Clock Fanout Buffer

The MC100ES8011H is a low voltage 1:2 Differential HSTL fanout buffer. Designed for the most demanding clock distribution systems, the

MC100ES8011H supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are in high performance clock distribution in computing, networking and telecommunication systems.Features••••••••••

1:2 differential clock fanout buffer20 ps maximum device skewSiGe Technology

Supports DC to 625 MHz operation

HSTL compatible differential clock outputsHSTL compatible differential clock inputs3.3V power supply

Supports industrial temperature rangeStandard 8 lead SOIC package8-lead Pb-free package available

MC100ES8011H

1:2 DIFFERENTIAL HSTLCLOCK FANOUT DRIVER

D SUFFIX8-LEAD SOIC PACKAGECASE 751-07EF SUFFIX8-LEAD SOIC PACKAGEPb-FREE PACKAGECASE 751-07ORDERING INFORMATION

VCC1

8Q0

Device

MC100ES8011HDMC100ES8011HDR2

D2

7Q0

MC100ES8011HEFMC100ES8011HEFR2

D3

6Q1

PinD, D

VEE4

5Q1

Qn, QnVCCVEE

PackageSO-8SO-8SO-8 (Pb-Free)SO-8 (Pb-Free)

PIN DESCRIPTION

FunctionHSTL Data InputsHSTL Data OutputsPositive SupplyNegative Supply

Figure1. 8-Lead Pinout (Top View) and Logic Diagram

© Freescale Semiconductor, Inc., 2005. All rights reserved.

Table 1. Absolute Maximum Ratings(1)

SymbolVSUPPLYVINIOUTTATSTG

Parameter

Power Supply VoltageInput VoltageOutput Current

Operating Temperature RangeStorage Temperature Range

Conditions

Difference between VCC & VEEVCC – VEE ≤ 3.6VContinuousSurge

Rating3.9VCC + 0.3VEE – 0.350100–40 to +85–65 to +150

UnitVVVmAmA°C°C

1.Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.

Table 2. DC Characteristics (VCC = 3.3 V ± 5%; TJ = 0°C to 110°C)(1)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

HSTL differential input signals (D, D)

VDIFVX, INIIN

Differential Input Voltage(2)Differential Cross Point Voltage(3)Input Current

0.20.25

0.68 – 0.9

VCC – 1.3±150

VVmA

VIN = VX ± 0.1V

HSTL clock outputs (Q[0:1], Q[0:1])VX, OUTVOHVOLICC

Output Differential CrosspointOutput High VoltageOuput Low Voltage

0.681

0.4

0.75

0.9

VVV

VCC pin (core)

Supply Current

Maximum Quiescent Supply Current without output termination current

80

105

mA

1.DC characteristics are design targets and pending characterization.

2.VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.

3.VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification.

MC100ES8011H2

Advanced Clock Drivers Devices

Freescale Semiconductor

Table 3. AC Characteristics (VCC = 3.3 V ± 5%; TJ = 0°C to 110°C)(1) (2)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

HSTL differential input signals (D, D)VDIFVX, INfCLKtPDVX, OUTVOHVOLVO(P-P)tSK(O)tSK(PP)tSK(P)tJIT(CC)tr / tf

Differential Input Voltage (peak-to-peak)(3)Differential Cross Point Voltage(4)Input Frequency

Propagation Delay D to Q[0:1}

700

920

0.40.68

0.96251200

VVMHzps

DifferentialDifferential

HSTL clock outputs (Q[0:1], Q[0:1])

Output Differential CrosspointOutput High VoltageOuput Low Voltage

Differential Output Voltage (peak-to-peak)Output-to-Output Skew

Output-to-Output Skew (part-to-part)Output Pulse SkewOutput Cycle-to-Cycle JitterOutput Rise/Fall Times

1500.5

205001001800

0.681

0.5

0.75

0.9

VVVVpspspspsps

20% to 80%DifferentialDifferential

1.AC characteristics are design targets and pending characterization.2.AC characteristics apply for parallel output termination of 50Ω to VTT.

3.VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.

4.VX (AC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew.

MC100ES8011H

Advanced Clock Drivers DevicesFreescale Semiconductor

3

Differential Pulse GeneratorZ = 50Ω

ZO = 50ΩZO = 50Ω

RT = 50ΩVTT=GND

DUT

MC100ES8011H

RT = 50Ω

VTT=GND

Figure 2. MC100ES8011H AC Test Reference

DDQ[0–1]Q[0–1]

VDIF=1.0V

VX=0.75V

tPD (D to Q[0–1])

Figure 3. MC100ES8011H AC Reference Measurement Waveform (HSTL Input)

MC100ES8011H4

Advanced Clock Drivers Devices

Freescale Semiconductor

PACKAGE DIMENSIONSPAGE 1 OF 2CASE 751-07ISSUE U

8-LEAD SOIC PACKAGE

MC100ES8011H

Advanced Clock Drivers DevicesFreescale Semiconductor

5

PACKAGE DIMENSIONSPAGE 2 OF 2CASE 751-07ISSUE U

8-LEAD SOIC PACKAGE

MC100ES8011H6

Advanced Clock Drivers Devices

Freescale Semiconductor

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MC100ES8011HRev. 209/2005

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