Delay circuit and method

专利名称：Delay circuit and method发明人：Hiroyuki Takahashi申请号：US09923997申请日：20010807公开号：US07042266B2公开日：20060509

专利附图：

摘要：A delay circuit does not lead to excessive increase in the delay time even if thesource voltage drops, and enables to control the delay time from increasing. The delaycircuit is designed to delay a logic signal SIN having two logic levels consisting of a lowlevel and a high level, such that the delay times are different for the high and low levels,

and the circuit chooses either the low level or the high level and targets a logic levelhaving a shorter delay time. That is, n-MOS transistors N, N and p-MOS transistors P, Pare provided as MOS capacitors, so as to change from the off-state to the on-stateduring the transition period of a signal that appears on each node disposed on a delaypath of logic signals. Such a circuit design enables to control source-voltage dependenceof delay time so that, even if the source voltage drops, delay times are not increasedexcessively.

申请人：Hiroyuki Takahashi

地址：Tokyo JP

国籍：JP

代理机构：Muirhead and Saturnelli, LLC

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