专利名称:Arrangements for Developing Integrated
Circuit Designs
发明人:William A. Binder,Ross B. Leavens,Sherwin C.
Murphy, JR.
申请号:US11934875申请日:20071105
公开号:US20090119630A1公开日:20090507
专利附图:
摘要:In some embodiments, a method is disclosed for converging on an acceptableintegrated circuit design for an integrated circuit. The method can include selecting a
path, determining if the path has a timing deficiency, segmenting the path into pathsegments and allocating the timing deficiency across the segments according toattributes of the path segments. Segments can have attributes such as a design freezewhen the design is mature or “optimum.” Allocating can include allocating the timingdeficiency across path segments according to attributes such as the proportion of thelength of a segmented path to the overall path length. Allocating can include allocatingthe timing deficiency to path segments based on attributes provided as user input.
申请人:William A. Binder,Ross B. Leavens,Sherwin C. Murphy, JR.
地址:Morrisville NC US,Cary NC US,Cary NC US
国籍:US,US,US
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