专利名称:Automated design analysis system for
generating circuit schematics from highmagnification images of an integrated circuit
发明人:Larry Lam,George Chamberlain,Alexei
Ioudovsky,Ghassan Naim
申请号:US08/420683申请日:19950412公开号:US05694481A公开日:19971202
摘要:A method of analyzing at least a portion of an integrated circuit (IC) comprisedof the steps of automatically: (a) scanning at least a portion of a layer of an integratedcircuit using high magnification to provide first digital signals representing pixelamplitudes, (b) extracting features of interest from the first digital signals to providesecond digital signals representing values of groups of pixels defining the features ofinterest, (c) modifying the second digital signals representing adjacent features ofinterest from step (b) so as to mosaic the features of interest and providing third signalsrepresenting a seamless representation of the layer, (d) repeating steps (a), (b) and (c)for other layers of the integrated circuit, whereby plural third signals representing pluralones of the layers are provided, (e) registering the plural third signals relative to eachother so as to represent vertical alignment of the layers by determining features ofinterest representative of IC mutual interconnection locations between layers, and usingthe locations as control points for the registering, and establishing an integrated circuitlayout database therefrom, (f) generating a netlist from data signals defining the cells,
and (g) generating a schematic diagram of a circuit contained in the integrated circuitfrom the netlist.
申请人:SEMICONDUCTOR INSIGHTS INC.
代理人:E. E. Pascal,R. A. Wilkes
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