元器件交易网www.cecb2b.comMC74HC4051A,MC74HC4052A,MC74HC4053AAnalogMultiplexers/DemultiplexersHigh–Performance Silicon–Gate CMOSThe MC74HC4051A, MC74HC4052A and MC74HC4053A utilizesilicon–gate CMOS technology to achieve fast propagation delays,low ON resistances, and low OFF leakage currents. These analogmultiplexers/demultiplexers control analog voltages that may varyacross the complete power supply range (from VCC to VEE).The HC4051A, HC4052A and HC4053A are identical in pinout tothe metal–gate MC14051AB, MC14052AB and MC14053AB. TheChannel–Select inputs determine which one of the AnalogInputs/Outputs is to be connected, by means of an analog switch, to theCommon Output/Input. When the Enable pin is HIGH, all analogswitches are turned off.The Channel–Select and Enable inputs are compatible with standardCMOS outputs; with pullup resistors they are compatible with LSTTLoutputs.These devices have been designed so that the ON resistance (Ron) ismore linear over input voltage than Ron of metal–gate CMOS analogswitches.For a multiplexer/demultiplexer with injection current protection,see HC4851A and HC4852A.•Fast Switching and Propagation Speeds•Low Crosstalk Between Switches•Diode Protection on All Inputs/Outputs•Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V•Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V•Improved Linearity and Lower ON Resistance Than Metal–GateCounterparts•Low Noise•In Compliance With the Requirements of JEDEC Standard No. 7A•Chip Complexity:HC4051A — 184 FETs or 46 Equivalent GatesHC4052A — 168 FETs or 42 Equivalent GatesHC4053A — 156 FETs or 39 Equivalent Gateshttp://onsemi.comMARKINGDIAGRAMS16161PDIP–16N SUFFIXCASE 648116SO–16D SUFFIXCASE 751B1HC405xANAWLYYWW161HC405xADAWLYYWW16161SO–16 WIDEDW SUFFIXCASE 751G1HC405xAAWLYWW16TSSOP–16DT SUFFIXCASE 948F116SOEIAJ–16F SUFFIXCASE 9661161HC405xAALYW1674HC405xAALYW1AWLYYWW= Assembly Location= Wafer Lot= Year= Work WeekORDERING INFORMATIONSee detailed ordering and shipping information in the packagedimensions section on page 13 of this data sheet.© Semiconductor Components Industries, LLC, 20001March, 2000 – Rev. 1Publication Order Number:MC74HC4051A/D元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AFUNCTION TABLE – MC74HC4051ALOGIC DIAGRAMMC74HC4051ASingle–Pole, 8–Position Plus Common OffX014X115X2ANALOG12MULTIPLEXER/INPUTS/X31DEMULTIPLEXEROUTPUTSX45X52X64X711ACHANNEL10BSELECT9INPUTSC6ENABLEPIN 16 = VCCPIN 7 = VEEPIN 8 = GND13Control InputsEnableLLLLLLLLHCLLLLHHHHXSelectBALLHHLLHHXLHLHLHLHXON ChannelsX0X1X2X3X4X5X6X7NONEX = Don’t Care3XCOMMONOUTPUT/INPUTPinout: MC74HC4051A (Top View)VCC16X215X114X013X312A11B10C91X42X63X4X75X567EnableVEE8GNDFUNCTION TABLE – MC74HC4052ALOGIC DIAGRAMMC74HC4052ADouble–Pole, 4–Position Plus Common OffX014X115X211X3Y0Y1Y2Y3AB1524109612Control InputsSelectEnableLLLLHX = Don’t CareBLLHHXALHLHXON ChannelsY0Y1Y2Y3NONEX0X1X2X3X SWITCH13XCOMMONOUTPUTS/INPUTSANALOGINPUTS/OUTPUTSY SWITCH3YPinout: MC74HC4052A (Top View)PIN 16 = VCCPIN 7 = VEEPIN 8 = GNDVCC16X215X114X13X012X311A10B9CHANNEL-SELECTINPUTSENABLE1Y02Y23Y4Y35Y167EnableVEE8GNDhttp://onsemi.com2元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AFUNCTION TABLE – MC74HC4053ALOGIC DIAGRAMMC74HC4053ATriple Single–Pole, Double–Position Plus Common OffX013X1Y01Y1Z03Z1A10CHANNEL-SELECTBINPUTS9C6ENABLE11521214Control InputsEnableLLLLLLLLHSelectCBALLLLHHHHXLLHHLLHHXLHLHLHLHXON ChannelsZ0Z0Z0Z0Z1Z1Z1Z1Y0Y0Y1Y1Y0Y0Y1Y1NONEX0X1X0X1X0X1X0X1X SWITCHXANALOGINPUTS/OUTPUTSY SWITCH15YCOMMONOUTPUTS/INPUTSZ SWITCH4ZX = Don’t CarePIN 16 = VCCPIN 7 = VEEPIN 8 = GNDPinout: MC74HC4053A (Top View)VCC16Y15X14X113X012A11B10C9NOTE: This device allows independent control of each switch.Channel–Select Input A controls the X–Switch, Input B controlsthe Y–Switch and Input C controls the Z–Switch1Y12Y03Z14Z5Z067EnableVEE8GNDMAXIMUM RATINGS*SymbolVCCVEEVISVinIParameterPositive DC Supply Voltage(Referenced to GND)(Referenced to VEE)Value– 0.5 to + 7.0– 0.5 to + 14.0– 7.0 to + 5.0VEE – 0.5 toVCC + 0.5UnitVVVVNegative DC Supply Voltage (Referenced to GND)Analog Input VoltageDigital Input Voltage (Referenced to GND)DC Current, Into or Out of Any PinPower Dissipation in Still Air,– 0.5 to VCC + 0.5±25750500450mAPDPlastic DIP†EIAJ/SOIC Package†TSSOP Package†mWThis device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high–impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v VCC.Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.TstgTLStorage Temperature Range– 65 to + 150260_C_CLead Temperature, 1 mm from Case for 10 SecondsPlastic DIP, SOIC or TSSOP Package*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.†Derating—Plastic DIP: – 10 mW/_C from 65_ to 125_CEIAJ/SOIC Package: – 7 mW/_C from 65_ to 125_CTSSOP Package: – 6.1 mW/_C from 65_ to 125_CFor high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).http://onsemi.com3元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053ARECOMMENDED OPERATING CONDITIONSSymbolVCCVEEVISVinParameterMin2.02.0MaxUnitVVVVVPositive DC Supply Voltage(Referenced to GND)(Referenced to VEE)6.012.0Negative DC Supply Voltage, Output (Referenced toGND)Analog Input Voltage– 6.0VEEGNDVCCVCC1.2Digital Input Voltage (Referenced to GND)Static or Dynamic Voltage Across SwitchGNDVIO*TAOperating Temperature Range, All Package TypesInput Rise/Fall Time(Channel Select or Enable Inputs)– 550000+ 1251000600500400_Cnstr, tfVCC = 2.0 VVCC = 3.0 VVCC = 4.5 VVCC = 6.0 V*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may bedrawn; i.e., the current out of the switch may contain both VCC and switch input components.The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where NotedSymbolVIHParameterMinimum High–Level InputVoltage, Channel–Select orEnable InputsMaximum Low–Level InputVoltage, Channel–Select orEnable InputsMaximum Input Leakage Current,Channel–Select or Enable InputsMaximum Quiescent SupplyCurrent (per Package)ConditionRon = Per SpecVCCV2.03.04.56.02.03.04.56.06.0Guaranteed Limit–55 to 25°C1.502.103.154.200.50.91.351.8±0.1≤85°C1.502.103.154.200.50.91.351.8±1.0≤125°C1.502.103.154.200.50.91.351.8±1.0UnitVVILRon = Per SpecVIinICCVin = VCC or GND,VEE = – 6.0 VChannel Select, Enable andVIS = VCC or GND;VEE = GNDVIO = 0 VVEE = – 6.0µAµA6.06.01410402080NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).http://onsemi.com4元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053ADC CHARACTERISTICS — Analog SectionGuaranteed LimitSymbolRonParameterMaximum “ON” ResistanceConditionVin = VIL or VIH; VIS = VCC toVEE; IS ≤ 2.0 mA(Figures 1, 2)Vin = VIL or VIH; VIS = VCC orVEE (Endpoints); IS ≤ 2.0 mA(Figures 1, 2)∆RonMaximum Difference in “ON”Resistance Between Any TwoChannels in the Same PackageMaximum Off–Channel LeakageCurrent, Any One ChannelVin = VIL or VIH;VIS = 1/2 (VCC – VEE);IS ≤ 2.0 mAVin = VIL or VIH;VIO = VCC – VEE;Switch Off (Figure 3)VCC4.54.56.04.54.56.04.54.56.06.06.06.06.06.06.06.0VEE0.0– 4.5– 6.00.0– 4.5– 6.00.0– 4.5– 6.0– 6.0– 6.0– 6.0– 6.0– 6.0– 6.0– 6.0–55 to 25°C190120100150100803012100.10.20.10.10.20.10.1≤85°C2401501251901251003515120.52.01.01.02.01.01.0≤125°C2801701402301401154018141.04.02.02.04.02.02.0µAΩUnitΩIoffµAMaximum Off–ChannelHC4051AVin = VIL or VIH;Leakage Current,HC4052AVIO = VCC – VEE;Common ChannelHC4053ASwitch Off (Figure 4)IonMaximum On–ChannelHC4051AVin = VIL or VIH;Leakage Current,HC4052ASwitch–to–Switch =Channel–to–ChannelHC4053AVCC – VEE; (Figure 5)AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)SymboltPLH,tPHLParameterMaximum Propagation Delay, Channel–Select to Analog Output(Figure 9)VCCV2.03.04.56.02.03.04.56.02.03.04.56.02.03.04.56.0Guaranteed Limit–55 to 25°C270905945402512101607048392451154939103513080501.0≤85°C3201107965603015132009563553151456958103513080501.0≤125°C35012585757032181522011076633451558367103513080501.0UnitnstPLH,tPHLMaximum Propagation Delay, Analog Input to Analog Output(Figure 10)nstPLZ,tPHZMaximum Propagation Delay, Enable to Analog Output(Figure 11)nstPZL,tPZHMaximum Propagation Delay, Enable to Analog Output(Figure 11)nsCinCI/OMaximum Input Capacitance, Channel–Select or Enable InputsMaximum Capacitance(All Switches Off)Analog I/OCommon O/I: HC4051AHC4052AHC4053AFeedthroughpFpFNOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor High–Speed CMOS Data Book (DL129/D)Typical @ 25°C, VCC = 5.0 V, VEE = 0 VCPDPower Dissipation Capacitance (Figure 13)*HC4051AHC4052AHC4053A458045pF*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High–Speed CMOS Data Book (DL129/D).http://onsemi.com5元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)SymbolBWParameterMaximum On–Channel Bandwidthor Minimum Frequency ResponseMiiFR(Figure 6)Conditionfin = 1MHz Sine Wave; Adjust fin Voltage toObti0dBObtain 0dBm at VtVOS; Increase fIfinFrequency Until dB Meter Reads –3dB;RL = 50Ω, CL = 10pFfin = Sine Wave; Adjust fin Voltage toObtain 0dBm at VISfin = 10kHz, RL = 600Ω, CL = 50pFVCCVVEEV‘512.254.506.002.254.506.002.254.506.002.254.506.002.254.506.002.254.506.002.254.506.00–2.25–4.50–6.00–2.25–4.50–6.00–2.25–4.50–6.00–2.25–4.50–6.00–2.25–4.50–6.00–2.25–4.50–6.00–2.25–4.50–6.00808080 Limit*25°C‘52959595–50–50–50–40–40–402510513535145190–50–50–50–60–60–60%2.254.506.00–2.25–4.50–6.000.100.080.05dBmVPP‘53120120120dBUnitMHz—Off–Channel Feedthrough Isolation(Figure 7)fin = 1.0MHz, RL = 50Ω, CL = 10pF—Feedthrough Noise.Channel–Select Input to CommonI/O (Figure 8)Vin ≤ 1MHz Square Wave (tr = tf = 6ns);Adjust RL at Setup so that IS = 0A; Enable = GNDRL = 600Ω, CL = 50pFRL = 10kΩ, CL = 10pF—Crosstalk Between Any TwoSwitches (Figure 12)(Test does not apply to HC4051A)fin = Sine Wave; Adjust fin Voltage toObtain 0dBm at VISfin = 10kHz, RL = 600Ω, CL = 50pFfin = 1.0MHz, RL = 50Ω, CL = 10pFTHDTotal Harmonic Distortion(Figure 14)fin = 1kHz, RL = 10kΩ, CL = 50pFTHD = THDmeasured – THDsourceVIS = 4.0VPP sine waveVIS = 8.0VPP sine waveVIS = 11.0VPP sine wave*Limits not tested. Determined by design and verified by qualification.300Ron, ON RESISTANCE (OHMS)Ron, ON RESISTANCE (OHMS)250200125°C15010050025°C–55°C1801601401201008060402000.250.50.751.01.251.51.752.02.25000.250.50.751.01.251.51.752.02.252.52.753.0VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE–55°C125°C25°CVIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEEFigure 1a. Typical On Resistance, VCC – VEE = 2.0 VFigure 1b. Typical On Resistance, VCC – VEE = 3.0 Vhttp://onsemi.com6元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053A120Ron, ON RESISTANCE (OHMS)Ron, ON RESISTANCE (OHMS)100806025°C40–55°C20000.51.01.52.02.53.03.54.04.5105907560453015000.51.01.52.02.53.03.54.04.55.05.56.0125°C25°C–55°C125°CVIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEEVIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEEFigure 1c. Typical On Resistance, VCC – VEE = 4.5 VFigure 1d. Typical On Resistance, VCC – VEE = 6.0 V80Ron, ON RESISTANCE (OHMS)Ron, ON RESISTANCE (OHMS)706050403020100–4.5–3.5–2.5–1.5–0.50.51.52.53.54.525°C–55°C125°C60504025°C30–55°C20100–6.0–5.0–4.0–3.0–2.0–1.0125°C01.02.03.04.05.06.0VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEEVIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEEFigure 1e. Typical On Resistance, VCC – VEE = 9.0 VFigure 1f. Typical On Resistance, VCC – VEE = 12.0 VPLOTTERPROGRAMMABLEPOWERSUPPLY–+MINI COMPUTERDC ANALYZERVCCDEVICEUNDER TESTANALOG INCOMMON OUTVEEGNDFigure 2. On Resistance Test Set–Uphttp://onsemi.com7元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AVCCVCCVEEOFFVCCANCOFF16VCCVEEVCCANALOG I/O16OFFOFFVCCCOMMON O/ICOMMON O/IVIH678VIH678VEEVEEFigure 3. Maximum Off Channel Leakage Current,Any One Channel, Test Set–UpFigure 4. Maximum Off Channel Leakage Current,Common Channel, Test Set–UpVCCAONVEEVCCANALOG I/OVIL678OFF16VCCN/Cfin0.1µFONVCC16VOSdBMETERCL*RLCOMMON O/I678VEE*Includes all probe and jig capacitanceVEEFigure 5. Maximum On Channel Leakage Current,Channel to Channel, Test Set–UpFigure 6. Maximum On Channel Bandwidth,Test Set–UpVIS0.1µFfinRLOFFVCC16VOSdBMETERCL*RLRLANALOG I/OOFF/ONRLON/OFFVCC16COMMON O/IRLCL*TESTPOINT678VEEVIL or VIHCHANNEL SELECT*Includes all probe and jig capacitanceVin ≤1 MHztr = tf = 6 nsVEEVCCGND678VCC11CHANNEL SELECT*Includes all probe and jig capacitanceFigure 7. Off Channel Feedthrough Isolation,Test Set–UpFigure 8. Feedthrough Noise, Channel Select toCommon Out, Test Set–Uphttp://onsemi.com8元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AVCCVCCCHANNELSELECTtPLHANALOGOUT50%50%GNDtPHL678CHANNEL SELECT*Includes all probe and jig capacitanceANALOG I/OOFF/ONCL*ON/OFFVCC16COMMON O/ITESTPOINTFigure 9a. Propagation Delays, Channel Selectto Analog OutFigure 9b. Propagation Delay, Test Set–Up ChannelSelect to Analog OutVCC16ANALOGINtPLHANALOGOUT50%VCC50%GNDtPHL678ANALOG I/OONCL*COMMON O/ITESTPOINT*Includes all probe and jig capacitanceFigure 10a. Propagation Delays, Analog Into Analog OutFigure 10b. Propagation Delay, Test Set–UpAnalog In to Analog OuttfENABLEtPZLANALOGOUT50%tr90%50%10%tPLZVCCGNDHIGHIMPEDANCE10%tPZHtPHZVOLVCC12POSITION 1 WHEN TESTING tPHZ AND tPZHPOSITION 2 WHEN TESTING tPLZ AND tPZLVCC16ANALOG I/OON/OFFCL*ENABLE6781kΩTESTPOINT12ANALOGOUT90%50%VOHHIGHIMPEDANCEFigure 11a. Propagation Delays, Enable toAnalog OutFigure 11b. Propagation Delay, Test Set–UpEnable to Analog Outhttp://onsemi.com9元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AVISRL0.1µFOFFVEERL678*Includes all probe and jig capacitanceRLCL*RLCL*VEE678VCC1116ONVCCVOSANALOG I/OOFF/ONON/OFFVCCA16COMMON O/INCfinCHANNEL SELECTFigure 12. Crosstalk Between Any TwoSwitches, Test Set–UpVIS0.1µFfinONRLCL*0VCC16VOSTODISTORTIONMETERdB–10–20–30–40–50–60678VEE*Includes all probe and jig capacitance–70–80–90–100Figure 13. Power Dissipation Capacitance, Test Set–UpFUNDAMENTAL FREQUENCYDEVICESOURCE1.02.0FREQUENCY (kHz)3.125Figure 14a. Total Harmonic Distortion, Test Set–UpFigure 14b. Plot, Harmonic DistortionAPPLICATIONS INFORMATIONThe Channel Select and Enable control pins should be atVCC or GND logic levels. VCC being recognized as a logichigh and GND being recognized as a logic low. In thisexample:VCC = +5V = logic highGND = 0V = logic lowThe maximum analog voltage swings are determined bythe supply voltages VCC and VEE. The positive peak analogvoltage should not exceed VCC. Similarly, the negative peakanalog voltage should not go below VEE. In this example,the difference between VCC and VEE is ten volts. Therefore,using the configuration of Figure 15, a maximum analogsignal of ten volts peak–to–peak can be controlled. Unusedanalog inputs/outputs may be left floating (i.e., notconnected). However, tying unused analog inputs andoutputs to VCC or GND through a low value resistor helpsminimize crosstalk and feedthrough noise that may bepicked up by an unused switch.Although used here, balanced supplies are not arequirement. The only constraints on the power supplies arethat:VCC – GND = 2 to 6 voltsVEE – GND = 0 to –6 voltsVCC – VEE = 2 to 12 voltsand VEE ≤ GNDWhen voltage transients above VCC and/or below VEE areanticipated on the analog channels, external Germanium orSchottky diodes (Dx) are recommended as shown in Figure16. These diodes should be able to absorb the maximumanticipated current surges during clipping.http://onsemi.com10元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053A+5V+5V–5VANALOGSIGNAL16ONANALOGSIGNAL+5V–5VVCCDxDxVEE678–5V11109TO EXTERNAL CMOSCIRCUITRY 0 to 5V DIGITAL SIGNALSVEEVCC16ON/OFFDxVEEVCCDx78Figure 15. Application ExampleFigure 16. External Germanium orSchottky Clipping Diodes+5V+5VVEE+5VVEEANALOGSIGNAL16ON/OFFANALOGSIGNAL+5VVEE+5VLSTTL/NMOSCIRCUITRYVEE67811109HCTBUFFERLSTTL/NMOSCIRCUITRY+5V+5VVEEANALOGSIGNAL16ON/OFFANALOGSIGNAL+5V*RRR678VEE11109* 2K ≤ R ≤ 10Ka. Using Pull–Up Resistorsb. Using HCT InterfaceFigure 17. Interfacing LSTTL/NMOS to CMOS Inputs11LEVELSHIFTER13AX014X1B10LEVELSHIFTER15X212X3C9LEVELSHIFTER1X45X5ENABLE6LEVELSHIFTER2X64X73Figure 18. Function Diagram, HC4051AXhttp://onsemi.com11元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AA10LEVELSHIFTER12X014X1B9LEVELSHIFTER15X21113ENABLE6LEVELSHIFTER1X3XY05Y12Y24Y33YFigure 19. Function Diagram, HC4052AA11LEVELSHIFTER13X11214B10LEVELSHIFTER1X0XY1215C9LEVELSHIFTER3Y0YZ154ENABLE6LEVELSHIFTERZ0ZFigure 20. Function Diagram, HC4053Ahttp://onsemi.com12元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053AORDERING & SHIPPING INFORMATIONDeviceMC74HC4051ANMC74HC4051ADMC74HC4051ADR2MC74HC4051ADTMC74HC4051ADTR2MC74HC4051ADWMC74HC4051ADWR2MC74HC4051AFMC74HC4051AFELMC74HC4052ANMC74HC4052ADMC74HC4052ADR2MC74HC4052ADTMC74HC4052ADTR2MC74HC4052ADWMC74HC4052ADWR2MC74HC4052AFMC74HC4052AFELMC74HC4053ANMC74HC4053ADMC74HC4053ADR2MC74HC4053ADTMC74HC4053ADTR2MC74HC4053ADWMC74HC4053ADWR2MC74HC4053AFMC74HC4053AFELPackagePDIP–16SOIC–16SOIC–16TSSOP–16TSSOP–16SOIC WIDESOIC WIDESOEIAJ–16SOEIAJ–16PDIP–16SOIC–16SOIC–16TSSOP–16TSSOP–16SOIC WIDESOIC WIDESOEIAJ–16SOEIAJ–16PDIP–16SOIC–16SOIC–16TSSOP–16TSSOP–16SOIC WIDESOIC WIDESOEIAJ–16SOEIAJ–16Shipping500 Units / Unit Pak48 Units / Rail2500 Units / Tape & Reel96 Units / Rail2500 Units / Tape & Reel48 Units / Rail1000 Units / Tape & ReelSee Note 1.See Note 1.500 Units / Unit Pak48 Units / Rail2500 Units / Tape & Reel96 Units / Rail2500 Units / Tape & Reel48 Units / Rail1000 Units / Tape & ReelSee Note 1.See Note 1.500 Units / Unit Pak48 Units / Rail2500 Units / Tape & Reel96 Units / Rail2500 Units / Tape & Reel48 Units / Rail1000 Units / Tape & ReelSee Note 1.See Note 1.1.For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.http://onsemi.com13元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053APACKAGE DIMENSIONSPDIP–16N SUFFIXCASE 648–08ISSUE R–A–169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMILLIMETERSMINMAXMINMAX0.7400.77018.8019.550.2500.2706.856.350.1450.1754.443.690.0150.0210.530.390.0400.0701.771.020.100 BSC2.54 BSC0.050 BSC1.27 BSC0.0080.0150.380.210.1100.1303.302.800.2950.3057.747.5010°0°10°0°0.0200.0401.010.51B18FSCLHKGD 16 PL0.25 (0.010)–T–SEATINGPLANEJTAMMMSOIC–16D SUFFIXCASE 751B–05ISSUE J–A–169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.DIMABCDFGJKMPRMILLIMETERSMINMAX9.8010.004.003.801.751.350.490.351.250.401.27 BSC0.250.190.250.107° 0°6.205.800.500.25INCHESMINMAX0.3860.3930.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090° 7° 0.2290.2440.0100.0191–B–8P 8 PL0.25 (0.010)MBMGFKCSEATING–PLANER X 45°–TMD16PL0.25 (0.010)MJTBSAShttp://onsemi.com14元器件交易网www.cecb2b.comMC74HC4051A, MC74HC4052A, MC74HC4053APACKAGE DIMENSIONSSOIC–16 WIDEDW SUFFIXCASE 751G–03ISSUE BD16M9AqNOTES:1.DIMENSIONS ARE IN MILLIMETERS.2.INTERPRET DIMENSIONS AND TOLERANCESPER ASME Y14.5M, 1994.3.DIMENSIONS D AND E DO NOT INLCUDE MOLDPROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5.DIMENSION B DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.13 TOTAL IN EXCESSOF THE B DIMENSION AT MAXIMUM MATERIALCONDITION.DIMAA1BCDEeHhLqMILLIMETERSMINMAX2.352.650.100.250.350.490.230.3210.1510.457.407.601.27 BSC10.0510.550.250.750.500.900 7 __HB116X8BTASBBS0.25MAhX 45_SEATINGPLANEM8X0.25EA114XeTC16X REFKTSSOP–16DT SUFFIXCASE 948F–01ISSUE OM0.10 (0.004)0.15 (0.006)TUSTUSVSLKK11692XL/2J1B–U–SECTION N–NJLPIN 1IDENT.18N0.15 (0.006)TUS0.25 (0.010)MA–V–NFDETAIL ENOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH.PROTRUSIONS OR GATE BURRS. MOLD FLASH ORGATE BURRS SHALL NOT EXCEED 0.15 (0.006) PERSIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.7.DIMENSION A AND B ARE TO BE DETERMINED ATDATUM PLANE –W–.MILLIMETERSMINMAX4.905.104.304.50–––1.200.050.150.500.750.65 BSC0.180.280.090.200.090.160.190.300.190.256.40 BSC0 8 __INCHESMINMAX0.1930.2000.1690.177–––0.0470.0020.0060.0200.0300.026 BSC0.0070.0110.0040.0080.0040.0060.0070.0120.0070.0100.252 BSC0 8 __C0.10 (0.004)–T–SEATINGPLANE–W–DGHDETAIL EDIMABCDFGHJJ1KK1LMhttp://onsemi.com15元器件交易网www.cecb2b.com
MC74HC4051A, MC74HC4052A, MC74HC4053A
PACKAGE DIMENSIONS
SOEIAJ–16F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01ISSUE O
169LEQ1EHEM_LDETAIL P18ZDeAVIEW PNOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASHOR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLEDAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWERRADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEADTO BE 0.46 ( 0.018).DIMAA1bcDEeHELLEMQ1ZMILLIMETERSMINMAX–––2.050.050.200.350.500.180.279.9010.505.105.451.27 BSC7.408.200.500.851.101.500 _10 _0.700.90–––0.78INCHESMINMAX–––0.0810.0020.0080.0140.0200.0070.0110.3900.4130.2010.2150.050 BSC0.2910.3230.0200.0330.0430.0590 _10 _0.0280.035–––0.031cb0.13 (0.005)MA10.10 (0.004)ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must bevalidated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury ordeath may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and holdSCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonableattorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claimalleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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