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K9F1208B0B

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K9F1208R0BK9F1208B0BK9F1208U0B

PreliminaryFLASH MEMORY

Document TitleM x 8 Bit NAND Flash Memory

Revision HistoryRevision No.History0.00.1

Initial issue.

1. Note 1 ( Program/Erase Characteristics) is added( page 14 )2. NAND Flash Technical Notes is changed.

-Invalid block -> initial invalid block ( page 16 ) -Error in write or read operation ( page 17 ) -Program Flow Chart ( page 17 )3. Vcc range is changed -2.4V~2.9V -> 2.5V~2.9V -1.7V~1.95V ->1.65V~1.95V

4. Multi plane operation and Copy-Back Program are not supported with 1.8V

device.

Draft DateApr. 24th 2004Oct. 11th.2004

RemarkAdvancePreliminary

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you haveany questions, please contact the SAMSUNG branch office near you.

K9F1208R0BK9F1208B0BK9F1208U0B

PreliminaryFLASH MEMORY

M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part NumberK9F1208R0B-G,JK9F1208B0B-Y,PK9F1208B0B-G,JK9F1208U0B-Y,PK9F1208U0B-G,JK9F1208U0B-V,F

2.7 ~ 3.6VVcc Range1.65 ~ 1.95V2.5 ~ 2.9V

PKG TypeFBGATSOP1FBGATSOP1FBGAWSOP1

FEATURES

• Voltage Supply

- 1.8V device(K9F1208R0B) : 1.65~1.95V - 2.7V device(K9F1208B0B) : 2.5~2.9V - 3.3V device(K9F1208U0B) : 2.7 ~ 3.6 V• Organization

- Memory Cell Array : (M + 2048K)bit x 8 bit - Data Register : (512 + 16)bit x 8bit• Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte• Page Read Operation

- Page Size : (512 + 16)Byte

- Random Access : 15µs(Max.) - Serial Page Access : 50ns(Min.)(*K9F1208R0B : tRC = 60ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.) - Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port• Hardware Data Protection

- Program/Erase Lockout During Power Transitions• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years• Command Register Operation• Intelligent Copy-Back

• Unique ID for Copyright Protection• Package

- K9F1208X0B-YCB0/YIB0

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - K9F1208X0B-GCB0/GIB0

63- Ball FBGA (8.5 x 13 , 1.0 mm width) - K9F1208U0B-VCB0/VIB0

48 - Pin WSOP I (12X17X0.7mm) - K9F1208X0B-PCB0/PIB0

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)- Pb-free Package - K9F1208X0B-JCB0/JIB0

63- Ball FBGA - Pb-free Package - K9F1208U0B-FCB0/FIB0

48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F1208U0B-V,F(WSOPI ) is the same device as K9F1208U0B-Y,P(TSOP1) except package type.

GENERAL DESCRIPTION

Offered in Mx8bit the K9F1208X0B is 512M bit with spare 16M bit capacity. The device is offered in 1.8V, 2.7V, 3.3V Vcc. ItsNAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performedin typical 200µs on the 528-byte page and an erase operation can be performed in typical 2ms on a 16K-byte block. Data in the pagecan be read out at 50ns(K9F1208R0B : 60ns) cycle time per byte. The I/O pins serve as the ports for address and data input/outputas well as command input. The on-chip write control automates all program and erase functions including pulse repetition, whererequired, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1208X0B′sextended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. TheK9F1208X0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable appli-cations requiring non-volatility.

K9F1208R0BK9F1208B0BK9F1208U0B

PIN CONFIGURATION (TSOP1)

K9F1208U0B-YCB0,PCB0/YIB0,PIB0N.CN.CN.CN.CN.CN.CR/B RECEN.CN.CVccVssN.CN.CCLEALEWEWPN.CN.CN.CN.CN.C

1234567101112131415161718192021222324

48474443424140393837363534333231302928272625

N.CN.CN.CN.CI/O7I/O6I/O5I/O4N.CN.CN.CVccVssN.CN.CN.CI/O3I/O2I/O1I/O0N.CN.CN.CN.C

PreliminaryFLASH MEMORY

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)48 - TSOP1 - 1220F

Unit :mm/Inch

0.10 MAX0.004 #48

(0.25)0.01012.400.488MAX#24

#25

1.00±0.050.039±0.002

0.250.010TYP18.40±0.100.724±0.004

+0.07520.00±0.200.787±0.008

0.20-0.03+0.07#1

0.008-0.0010.16-0.03+0.07+0.0030.500.019712.000.4720.05

0.002MIN

0.1250.0350~8°0.45~0.750.018~0.030(0.50)0.0203

0.005-0.001+0.0031.20

0.047MAX

Package DimensionsPIN CONFIGURATION (WSOP1)K9F1208U0B-VCB0,FCB0/VIB0,FIB0N.CN.CDNUN.CN.CN.CR/B RECEDNUN.CVccVssN.CDNUCLEALEWEWPN.CN.CDNUN.CN.C123456710111213141516171819202122232448474443424140393837363534333231302928272625N.CN.CDNUN.CI/O7I/O6I/O5I/O4N.CDNUN.CVccVssN.CDNUN.CI/O3I/O2I/O1I/O0N.CDNUN.CN.CFLASH MEMORYPACKAGE DIMENSIONS48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)48 - WSOP1 - 1217F Unit :mm0.70 MAX15.40±0.100.58±0.04#1+0.07-0.03#48+0.07-0.030.1612.40MAX12.00±0.100.50TYP(0.50±0.06)0.20#24#25(0.01Min)0.0750.10+-0.0350°~8°0.45~0.7517.00±0.204K9F1208R0BK9F1208B0BK9F1208U0B

PIN CONFIGURATION (FBGA)

K9F1208X0B-GCB0,JCB0/GIB0,JIB0

1 2

N.CN.C

Preliminary

FLASH MEMORY

3456

N.CN.CN.CN.C

ABC

N.C

/WPNCNCNCNCNCNCVss

ALE/RENCNCNCI/O0I/O1I/O2

VssCLENCNCNCNCNC

/CENCNCNCNCNC

/WENCNCNCNCNC

R/BNCNCNCNCVccI/O7Vss

DEFGH

VccQI/O5

I/O6

I/O3I/O4

N.CN.CN.CN.C

Top View

Package Dimensions

63-Ball FBGA (measured in millimeters)

FLASH MEMORY

Top ViewBottom View

#A1 INDEX MARK(OPTIONAL)

8.50±0.10

68.50±0.100.80 x 9= 7.20 0.80 x 5= 4.00 0.8032

A1B#A1

(Datum A)AB

0.80 x 7= 5.60 2.000.45±0.05

1.00(Max.)0.25(Min.)CDE

0.80 x 11= 8.80 (Datum B)0.8013.00±0.102.80FGH63-∅0.45±0.05

∅0.20 M A B Side View

13.00±0.10

0.10MAX

13.00±0.10K9F1208R0BK9F1208B0BK9F1208U0B

PIN DESCRIPTION

Pin NameI/O0 ~ I/O7(K9F1208X0B)

Pin Function

PreliminaryFLASH MEMORY

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.WRITE ENABLE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.

WRITE PROTECT

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.OUTPUT BUFFER POWER

VccQ is the power supply for Output Buffer.

VccQ is internally connected to Vcc, thus should be biased to Vcc.POWER

VCC is the power supply for device. GROUND

NO CONNECTION

Lead is not internally connected.DO NOT USE

Leave it disconnected.

CLE

ALE

R/B

VccQ

VccVssN.CDNU

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

K9F1208R0BK9F1208B0BK9F1208U0BFigure 1-1. K9F1208X0B FUNCTIONAL BLOCK DIAGRAMVCCVSSA9 - A25X-BuffersLatches& DecodersY-BuffersLatches& DecodersPreliminaryFLASH MEMORY512M + 16M BitNAND FlashARRAYA0 - A7(512 + 16)Byte x 131072 Page Register & S/AA8CommandCommandRegisterY-GatingI/O Buffers & LatchesVCC/VCCQVSSOutputDriverI/0 0I/0 7CEREWEControl Logic& High VoltageGeneratorGlobal BuffersCLEALEWPFigure 2-1. K9F1208X0B ARRAY ORGANIZATION1 Block =32 Pages= (16K + 512) Byte 128K Pages(=4,096 Blocks)1st half Page Register(=256 Bytes)2nd half Page Register(=256 Bytes)1 Page = 528 Byte1 Block = 528 Byte x 32 Pages = (16K + 512) Byte1 Device = 528Bytes x 32Pages x 4096 Blocks = 528 Mbits8 bit16 Byte 512BytePage Register 512 ByteI/O 01st Cycle2nd Cycle3rd Cycle4th CycleA0A9A17A25I/O 1A1A10A18*LI/O 2A2A11A19*L16 ByteI/O 3A3A12A20*LI/O 0 ~ I/O 7I/O 4A4A13A21*LI/O 5A5A14A22*LI/O 6A6A15A23*LI/O 7A7A16A24*LColumn AddressRow Address(Page Address)NOTE : Column Address : Starting Address of the Register.00h Command(Read) : Defines the starting address of the 1st half of the register.01h Command(Read) : Defines the starting address of the 2nd half of the register.* A8 is set to \"Low\" or \"High\" by the 00h or 01h Command.* L must be set to \"Low\".* The device ignores any additional input of address cycles than reguired.8K9F1208R0BK9F1208B0BK9F1208U0B

Product Introduction

PreliminaryFLASH MEMORY

The K9F1208X0B is a 528Mbit(553,8,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columnsare located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating datatransfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of twoNAND structured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization isshown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a blockbasis. The memory array consists of 4,096 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is pro-hibited on the K9F1208X0B.

The K9F1208X0B has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgradesto future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's bybringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address LatchEnable(ALE) are used to multiplex command and address respectively, via the I/O pins. The M byte physical space requires 26addresses, thereby requiring four cycles for byte-level addressing: column address, low row address and high row address, in thatorder. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into thecommand register. Table 1 defines the specific commands of the K9F1208X0B.

The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into four 128Mbitseparate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintainingthe conventional 512 byte structure.

The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out ofselected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to anotherof the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burst-reading and data-input cycles are removed, system performance for solid-state disk application is significantly increased.

The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provideidentification capabilities. Detailed information can be obtained by contact with Samsung.

Table 1. Command Sets

Function

Read 1Read 2Read IDReset

Page Program (True)(2)Page Program (Dummy)(2)Copy-Back Program(True)(2)Copy-Back Program(Dummy)(2)Block Erase

Multi-Plane Block EraseRead Status

Read Multi-Plane Status

1st. Cycle00h/01h(1)

50h90hFFh80h80h00h03h60h60h----60h

70h71h(3)

2nd. Cycle

----10h11h8Ah8AhD0hD0h--3rd. Cycle

------10h11h----OOO

Acceptable Command

during Busy

NOTE : 1. The 00h command defines starting address of the 1st half of registers.

The 01h command defines starting address of the 2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer isautomatically moved to the 1st half register(00h) on the next cycle.

2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation.

Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd,3rd,4th plane of multi plane operation. 3. The 71h command should be used for read status of Multi Plane operation.

4. Multi plane operation and Copy-Back Program are not supported with 1.8V device.Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

K9F1208R0BK9F1208B0BK9F1208U0BMemory MapPreliminaryFLASH MEMORYThe device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows itto perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map isconfigured so that multi-plane program/erase operations can be executed for every four sequential blocks.Figure 3. Memory Array MapPlane 0(1024 Block)Plane 1(1024 Block)Plane 2(1024 Block)Plane 3(1024 Block)Block 0Page 0Page 1Block 1Page 0Page 1Block 2Page 0Page 1Block 3Page 0Page 1Page 30Page 31Block 4Page 0Page 1Page 30Page 31Block 5Page 0Page 1Page 30Page 31Block 6Page 0Page 1Page 30Page 31Block 7Page 0Page 1Page 30Page 31Page 30Page 31Page 30Page 31Page 30Page 31Block 4088Page 0Page 1Block 40Page 0Page 1Block 4090Page 0Page 1Block 4091Page 0Page 1Page 30Page 31Block 4092Page 0Page 1Page 30Page 31Block 4093Page 0Page 1Page 30Page 31Block 4094Page 0Page 1Page 30Page 31Block 4095Page 0Page 1Page 30Page 31Page 30Page 31Page 30Page 31Page 30Page 31528byte Page Registers528byte Page Registers528byte Page Registers528byte Page Registers10K9F1208R0BK9F1208B0BK9F1208U0B

ABSOLUTE MAXIMUM RATINGS

Parameter

SymbolVIN/OUT

Voltage on any pin relative to VSS

VCCVCCQ

Temperature Under BiasStorage TemperatureShort Circuit Current

K9F1208X0B-XCB0K9F1208X0B-XIB0K9F1208X0B-XCB0K9F1208X0B-XIB0

TBIASTSTGIos

Rating

1.8V DEVICE-0.6 to + 2.45-0.2 to + 2.45-0.2 to + 2.45

-10 to +125-40 to +125-65 to +150

PreliminaryFLASH MEMORY

3.3V/2.7V DEVICE

-0.6 to + 4.6-0.6 to + 4.6-0.6 to + 4.6

Unit

°C°CmA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, K9F1208X0B-XCB0 :TA=0 to 70°C, K9F1208X0B-XIB0:TA=-40 to 85°C)

ParameterSupply VoltageSupply VoltageSupply Voltage

SymbolVCCVCCQVSS

K9F1208R0B(1.8V)Min1.651.650

Typ.1.81.80

Max1.951.950

K9F1208B0B(2.7V)Min2.52.50

Typ.2.72.70

Max2.92.90

K9F1208U0B(3.3V)Min2.72.70

Typ.3.33.30

Max3.63.60

UnitVVV

K9F1208R0BK9F1208B0BK9F1208U0B

PreliminaryFLASH MEMORY

K9F1208X0B

Unit

3.3V

Max

Min

Typ

Max

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter

Symbol

Test Conditions

Min

tRC=50ns

(K9F1208R0B : 60ns), CE=VILIOUT=0mA

--CE=VIH, WP=0V/VCCCE=VCC-0.2, WP=0V/VCCVIN=0 to Vcc(max)VOUT=0 to Vcc(max)I/O pins

Input High Voltage

VIH*

Except I/O pins

Input Low Voltage, All inputs

Output High Voltage Level

VIL*

-K9F1208R0B :IOH=-100µAVOH

K9F1208B0B :IOH=-100µAK9F1208U0B :IOH=-400µAK9F1208R0B :IOL=100uA

Output Low Voltage Level

VOL

K9F1208B0B :IOL=100µAK9F1208U0B :IOL=2.1mAK9F1208R0B :VOL=0.1V

Output Low Current(R/B)

IOL(R/B)K9F1208B0B :VOL=0.1V

K9F1208U0B :VOL=0.4V

NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.

1.8VTyp

Max

Min

2.7VTyp

Sequential Read

Operating Current

ProgramErase

Stand-by Current(TTL)Stand-by Current(CMOS)Input Leakage CurrentOutput Leakage Current

ICC1-815-1020-1020

ICC2ICC3ISB1ISB2ILIILO

------VCCQ-0.4VCC-0.4-0.3VCCQ-0.1

88-10-----

1515150±10±10+0.3VCC+0.30.4

-------0.4VCC-0.4-0.3VCCQ-0.4

1010-10-----

2020150±10±10VCCQ+0.3VCC+0.30.5

------2.02.0-0.3

1010-10-----

2020150±10±10VCCQ+0.3VCC+0.30.8

µA

VCCQVCCQ

----2.4

--0.1--0.4--0.4

34-34-810-mA

K9F1208R0BK9F1208B0BK9F1208U0B

VALID BLOCK

Parameter

Valid Block Number

SymbolNVB

Min4,026

Typ.-

PreliminaryFLASH MEMORY

Max4,096

UnitBlocks

NOTE :

1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or programfactory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erasecycles.

3. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.

AC TEST CONDITION

(K9F1208X0B-XCB0 :TA=0 to 70°C, K9F1208X0B-XIB0:TA=-40 to 85°C

K9F1208R0B : Vcc=1.65V~1.95V , K9F1208B0B : Vcc=2.5V~2.9V , K9F1208U0B : Vcc=2.7V~3.6V unless otherwise noted)

Parameter

Input Pulse LevelsInput Rise and Fall TimesInput and Output Timing Levels

K9F1208R0B:Output Load (VccQ:1.8V +/-10%)K9F1208B0B:Output Load (VccQ:2.7V +/-10%)K9F1208U0B:Output Load (VccQ:3.0V +/-10%)K9F1208U0B:Output Load (VccQ:3.3V +/-10%)

K9F1208R0B0V to VccQ

5nsVccQ/2

K9F1208B0B0V to VccQ

5nsVccQ/2

K9F1208U0B0.4V to 2.4V

5ns1.5V

1 TTL GATE and CL=30pF1 TTL GATE and CL=30pF1 TTL GATE and CL=50pF

--1 TTL GATE and CL=100pF

CAPACITANCE(TA=25°C, VCC=1.8V/2.7V/3.3V, f=1.0MHz)

Item

Input/Output CapacitanceInput Capacitance

SymbolCI/OCIN

Test Condition

VIL=0VVIN=0V

Min--Max1010

UnitpFpF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLEHLHLLLLXXXXX

ALELHLHLLLXXXX(1)X

CELLLLLLLXXXXH

HHXXXXX

HHXXXX

REHHHHH

WPXXHHHXXXHHL

Read ModeWrite Mode Data Input Data Output

During Read(Busy) on K9F1208X0B-Y,P or K9F1208U0B-V,FDuring Read(Busy) on the devices except K9F1208X0B-Y,P and K9F1208U0B-V,F During Program(Busy) During Erase(Busy) Write Protect

Mode

Command Input Address Input(4clock) Command Input Address Input(4clock)

0V/VCC(2) Stand-by

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

K9F1208R0BK9F1208B0BK9F1208U0B

PROGRAM / ERASE CHARACTERISTICS

Parameter

Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cyclesin the Same PageBlock Erase Time

Main ArraySpare Array

SymboltPROG(1)tDBSYNoptBERS

---Min-Typ2001--2

PreliminaryFLASH MEMORY

Max50010123

Unitµsµscyclecyclesms

NOTE : 1.Typical program time is defined as the time within more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C

AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT

ParameterCLE setup TimeCLE Hold TimeCE setup TimeCE Hold TimeWE Pulse WidthALE setup TimeALE Hold TimeData setup TimeData Hold TimeWrite Cycle TimeWE High Hold Time

SymboltCLStCLHtCStCHtWP(1)tALStALHtDStDHtWCtWH

Min

1.8V0100104001020106020

2.7V0100102501020104515

3.3V0100102501020104515

1.8V-----------Max2.7V-----------3.3V-----------Unitnsnsnsnsnsnsnsnsnsnsns

NOTE: 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. 2. TBD means \"To Be Determinded\".

K9F1208R0BK9F1208B0BK9F1208U0B

AC CHARACTERISTICS FOR OPERATION

Parameter

Data Transfer from Cell to RegisterALE to RE DelayCLE to RE DelayReady to RE LowRE Pulse WidthWE High to BusyRead Cycle TimeRE Access TimeCE Access TimeRE High to Output Hi-ZCE High to Output Hi-ZRE or CE High to Output hold RE High Hold TimeOutput Hi-Z to RE LowWE High to RE Low

Device resetting time(Read/Program/Erase)

SymboltRtARtCLRtRRtRPtWBtRCtREAtCEAtRHZtCHZtOHtREHtIRtWHRtRST

Min

1.8V

2.7V

3.3V

1.8V

PreliminaryFLASH MEMORY

Max

2.7V

3.3V

Unitµsnsnsnsnsnsnsnsnsnsnsnsnsnsnsµs

-10102040-60----1520060-

-10102025-50----1515060-

-10102025-50----1515060

15----100-40553020----

15----100-30453020----

5/10/500(1)5/10/500(1)5/10/500(1)

Parameter

Last RE High to Busy(at sequential read)

K9F1208X0B-Y,V,P,F only

CE High to Ready(in case of interception by CE at read)CE High Hold Time(at the last serial read)(2)

SymboltRBtCRYtCEH

Min--100

Max10050 +tr(R/B)(3)

Unitnsnsns

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. To break the sequential read cycle, CE must be held high for longer time than tCEH. 3. The time to Ready depends on the value of the pull-up resistor tied R/B pin.ting time. 4. TBD means \"To Be Determinded\".

K9F1208R0BK9F1208B0BK9F1208U0B

NAND Flash Technical Notes

Initial Invalid Block(s)

PreliminaryFLASH MEMORY

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalidblock(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalidblock(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by aselect transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which isplaced on 00h block address, is guaranteed to be a valid block, does not require Error Correction up to 1K program/erase cycles.

Identifying Initial Invalid Block(s)

All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. Theinitial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page ofevery initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasablein most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognizethe initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following sug-gested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

* Check \"FFh\" ?

Check \"FFh\" at the column address517of the 1st and 2nd page in the block

NoCreate (or update)

Initial Invalid Block(s) Table

Yes

Last Block ?

Yes

End

Figure 4. Flow chart to create initial invalid block table.

K9F1208R0BK9F1208B0BK9F1208U0B

NAND Flash Technical Notes (Continued)

Error in write or read operation

PreliminaryFLASH MEMORY

Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the blockfailure rete.The following possible failure modes should be considered to implement a highly reliable system. In the case of statusread failure after erase or program, block replacement should be done. Because program status fail during a page program does notaffect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erasedempty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must beemployed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should bereclaimed by ECC without any block replacement. The block failure rate in thequalification report does not include those reclaimedblocks.

Failure Mode

Write Read

Erase Failure Program Failure Single Bit Failure

Detection and Countermeasure sequence

Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction

ECC: Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bit detection

Program Flow Chart Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

I/O 6 = 1 ?or R/B = 1 ?

Yes

I/O 0 = 0 ?

*Program Error Yes

Program Completed

* : If program operation results in an error, map outthe block including the page in error and copy the

target data to another block.

K9F1208R0BK9F1208B0BK9F1208U0BNAND Flash Technical Notes (Continued)Erase Flow Chart StartWrite 60hWrite Block AddressWrite D0hRead Status RegisterPreliminaryFLASH MEMORYRead Flow Chart StartWrite 00hWrite AddressRead DataECC GenerationI/O 6 = 1 ?or R/B = 1 ?YesNoI/O 0 = 0 ? Yes Erase CompletedNoReclaim the Error NoVerify ECC Yes Page Read Completed*Erase Error * : If erase operation results in an error, map outthe failing block and replace it with another block. Block Replacement1st(n-1)thnth(page)Block B1{{Block A2 an error occurs. Buffer memory of the controller.1st(n-1)thnth(page)* Step1When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’)* Step3Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.* Step4Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.∼∼18K9F1208R0BK9F1208B0BK9F1208U0B

Pointer Operation of K9F1208X0B

PreliminaryFLASH MEMORY

Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command setsthe pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a wholepage(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effectiveonly for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, theaddress pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputtedbefore ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from’B’ area, ’01h’ command must be inputted right before ’80h’ command is written.

Table 2. Destination of the pointer

Command

00h01h50h

Pointer position0 ~ 255 byte256 ~ 511 byte512 ~ 527 byte

Area1st half array(A)2nd half array(B)spare array(C)

\"A\" area(00h plane)256 Byte

\"B\" area(01h plane)256 Byte

\"C\" area(50h plane)16 Byte

\"A\"\"B\"\"C\"

InternalPage Register

Pointer selectcommnad

(00h, 01h, 50h)

Pointer

Figure 5. Block Diagram of Pointer Operation

(1) Command input sequence for programming ’A’ area

The address pointer is set to ’A’ area(0~255), and sustained

Address / Data input

00h

80h

10h

00h

80h

Address / Data input

10h

’A’,’B’,’C’ area can be programmed.

It depends on how many data are inputted.

’00h’ command can be omitted.

(2) Command input sequence for programming ’B’ area

The address pointer is set to ’B’ area(256~511), and will be reset to’A’ area after every program operation is executed.

Address / Data input

01h

80h

10h

01h

80h

Address / Data input

10h

’B’, ’C’ area can be programmed.

It depends on how many data are inputted.’01h’ command must be rewritten beforeevery program operation

(3) Command input sequence for programming ’C’ area

The address pointer is set to ’C’ area(512~527), and sustained

Address / Data input

50h

80h

10h

50h

80h

Address / Data input

10h

Only ’C’ area can be programmed.’50h’ command can be omitted.

K9F1208R0BK9F1208B0BK9F1208U0BSystem Interface Using CE don’t-care. PreliminaryFLASH MEMORYFor an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, forvoice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and readingwould provide significant savings in power consumption.Figure 7. Program Operation with CE don’t-care. CLECE don’t-care CE≈WEALE80hStart Add.(4Cycle)I/OXData Input Data Input ≈10htCSCEtCHCEtCEAtWPWEREtREAI/OXoutFigure 8. Read Operation with CE don’t-care. CLECEOn K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during tRCE don’t-care REALER/BtRWEI/OXData Output(sequential)00hStart Add.(4Cycle)20≈K9F1208R0BK9F1208B0BK9F1208U0BDeviceK9F1208X0BI/OI/OxI/O 0 ~ I/O 7PreliminaryFLASH MEMORYDATAData In/Out~528byteCommand Latch CycleCLEtCLStCSCEtCLHtCHtWPWEtALSALEtDSI/OXtALHtDHCommandAddress Latch CycletCLSCLEtCSCEtWCtWCtWCtWPWEtALSALEtDSI/OXtDHtWHtALHtALStWPtWHtALHtALStWPtWHtALHtALStWPtALHtDStDHtDStDHtDSA25tDHA0~A7A9~A16A17~A2421K9F1208R0BK9F1208B0BK9F1208U0BInput Data Latch CycletCLHCLEPreliminaryFLASH MEMORYtCHCEtALSALEtWCWEtDSI/OxtWHtDHtDStDH≈tWPtWPtWPtDHtDS≈DIN 0DIN 1DIN ntRCSerial access Cycle after Read(CLE=L, WE=H, ALE=L)≈CEtREARE≈tREHtCHZ*tREAtOH≈tREAtRHZ*I/OxtRRR/BDouttRHZ*tOHDoutDoutNOTES : Transition is measured ±200mV from steady state voltage with load.This parameter is sampled and not 100% tested.22≈≈K9F1208R0BK9F1208B0BK9F1208U0BStatus Read CycletCLRCLEtCLStCSCEtCHtCEAtWHRREtDSI/OX70htDHtIRtREAtCLHPreliminaryFLASH MEMORYtWPWEtCHZtOHtRHZtOHStatus OutputREAD1 OPERATION (READ ONE PAGE)CLE1)CEtWCWEtWBALE≈≈On K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during tRtCEHtCHZtOH≈≈≈tARtRHZtOHtCRYtRREN AddresstRRI/OX00h or 01h A0 ~ A7A9 ~ A16 A17 ~ A24A25Dout NtRC≈Dout N+1Dout N+2≈≈≈≈Dout m1)ColumnAddressPage(Row)AddressBusytRB1)X8 device : m = 528 , Read CMD = 00h or 01h NOTES : 1) is only valid on K9F1208X0B-Y,P or K9F1208X0B-V,F≈23R/BK9F1208R0BK9F1208B0BK9F1208U0BRead1 Operation (Intercepted by CE)CLEPreliminaryFLASH MEMORYCEWEtWBALE≈≈≈ On K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during tR≈≈tARtCHZtOHtRCtRREtRRI/OX00h or 01hA0 ~ A7A9 ~ A16A17 ~ A24≈≈ A25Dout NDout N+1Dout N+2ColumnAddressPage(Row)AddressBusyRead2 Operation (Read One Page)CLE On K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during tRCEWEtWBALE≈R/BtRtARtRRREI/OX50hA0 ~ A7A9 ~ A16A17 ~ A24A25Dout n+M≈≈n+mR/BM AddressA0~A3 : Valid AddressA4~A7 : Don′t care SelectedRow51216 Startaddress M24K9F1208R0BK9F1208B0BK9F1208U0BSequential Row Read Operation (Within a Block)CLEPreliminaryFLASH MEMORYWE≈ALE≈≈CE≈≈≈REI/OX00hA0 ~ A7A9 ~ A16A17 ~ A24 A25DoutNDoutN+1≈Dout527Dout0Dout1≈Dout527≈≈MM+1≈R/BBusy≈Busy≈Output70hRead StatusCommandI/O0I/O0=0 Successful ProgramI/O0=1 Error in ProgramReadyNOutputPage Program OperationCLECEWEtWBALEtPROGREDinDin10hN5271 up to 528 Byte DataProgramCommandSerial InputI/OX80hA0 ~ A7A9 ~ A16A17 ~ A24Page(Row)AddressA25Sequential DataColumnInput CommandAddress25≈R/B≈≈≈tWCtWCtWC≈≈≈K9F1208R0BK9F1208B0BK9F1208U0BBLOCK ERASE OPERATION (ERASE ONE BLOCK)PreliminaryFLASH MEMORYCLECEtWCWEtWBALEtBERSREI/OX60hA9 ~ A16A17 ~ A24Page(Row)AddressA25DOh70hI/O 0R/BAuto Block Erase Setup CommandErase CommandBusyRead StatusCommandI/O0=0 Successful EraseI/O0=1 Error in Erase26Multi-Plane Page Program Operation K9F1208R0BK9F1208B0BK9F1208U0BtWC≈≈≈≈WEtWBtDBSYtWBtPROG≈≈RE≈≈≈ALE≈≈≈≈CE≈≈CLE≈≈≈≈I/OX80hA0 ~ A7A9 ~ A16A17 ~ A24A2511hProgram1 up to 528 Byte DataCommand(Dummy)Serial Input80hA0 ~ A7A9 ~ A16A17 ~ A24DinNDinNDinmDin527≈A2571h10hProgram ConfirmCommand(True)I/OMax. three times repeatable≈Last Plane Input & Program D B S Y t: typ. 1us max. 10usEx.) Four-Plane Page ProgramtDBSYtDBSYtDBSYtPROGR/B11h80h Address & Data Input≈2711h80h Address & Data InputA0 ~ A7 & A9 ~ A25528 Byte DataA0 ~ A7 & A9 ~ A25528 Byte Data11hSequential DataInput CommandColumnAddressPage(Row)AddressRead Multi-Plane Status CommandR/BI/O0~780h Address & Data Input80h Address & Data InputA0 ~ A7 & A9 ~ A25528 Byte Data10h71hPreliminaryFLASH MEMORYA0 ~ A7 & A9 ~ A25528 Byte DataK9F1208R0BK9F1208B0BK9F1208U0BMulti-Plane Block Erase OperationPreliminaryFLASH MEMORYCLECEtWCWEtWBALEtBERSREI/OX60hA9 ~ A16A17 ~ A24Page(Row)AddressA25DOh71hI/O 0R/B Block Erase Setup CommandErase Confirm CommandBusyRead Multi-Plane StatusCommandMax. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before \"D0H\" command. Ex.) Four-Plane Block Erase OperationR/BI/O0~760h Address A9 ~ A2560hA9 ~ A25 60hA9 ~ A2560hA9 ~ A25D0htBERS71h 28K9F1208R0BK9F1208B0BK9F1208U0B

Read ID Operation

PreliminaryFLASH MEMORY

CLE

ALE

tREA

I/OX

90h

Read ID Command

00hAddress. 1cycle

EChMaker Code

DeviceCode

A5h

C0hMulti Plane Code

DeviceK9F1208R0BK9F1208B0BK9F1208U0B

Device Code

36h76h76h

ID Defintition Table

90 ID : Access command = 90H

Description

1st Byte2nd Byte3rd Byte4th Byte

Maker CodeDevice Code

Must be don’t -cared

Supports Multi Plane Operation(Must be don’t-cared for 1.8 device)

K9F1208R0BK9F1208B0BK9F1208U0BCopy-Back Program Operation PreliminaryFLASH MEMORYCEtWCWEtWB On K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during tRtWBtPROGtRRE≈≈ALE≈I/OX00hA0~A7A9~A16A17~A24ColumnAddressPage(Row)AddressA258AhA0~A7A9~A16A17~A24ColumnAddressPage(Row)AddressA2510h≈≈≈70h≈≈≈≈≈≈≈≈≈≈≈CLEI/O0Read StatusCommand≈Copy-Back DataInput CommandI/O0=0 Successful ProgramI/O0=1 Error in Program30≈R/BBusyBusyK9F1208R0BK9F1208B0BK9F1208U0B

Device Operation

PAGE READ

PreliminaryFLASH MEMORY

Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis-ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation.Three types of operations are available : random read, serial page read and sequential row read.

The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferredto the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing theoutput of R/B pin. CE must be held low while in busy for K9F1208U0B-YXB0 or K9F1208U0B-VXB0, while CE is don’t-care withK9F1208X0B-GXB0 or K9F1208X0B-JXB0. If CE goes high before the device returns to Ready, the random read operation is inter-rupted and Busy returns to Ready as the defined by tCRY. Since the operation was aborted, the serial page read does not output validdata. Once the data in a page is loaded into the registers, they may be read out in 50ns(K9F1208R0B : 60ns) cycle time by sequen-tially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last col-umn address.

The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512to 527 bytes may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the sparearea while addresses A4 to A7 are ignored. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Fig-ures 7 to 10 show typical sequence and timings for each read operation.

Sequential Row Read is available only on K9F1208X0B-Y,P or K9F1208U0B-V,F :

After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 15µsagain allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operationis aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes ofeach page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page ofa block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto thenext block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row readoperation.

K9F1208R0BK9F1208B0BK9F1208U0BFigure 7. Read1 OperationCLECEWEALER/BREI/O0~700hStart Add.(4Cycle)(00h Command)Main arrayPreliminaryFLASH MEMORY On K9F1208U0B-Y,P or K9F1208U0B-V,F CE must be held low during tRtRData Output(Sequential) A0 ~ A7 & A9 ~ A251)(01h Command)1st half array2st half arrayData FieldSpare FieldData FieldSpare FieldNOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 32K9F1208R0BK9F1208B0BK9F1208U0BFigure 8. Read2 OperationCLECEWEALER/BREI/OX50hStart Add.(4Cycle)PreliminaryFLASH MEMORY On K9F1208U0B-Y,P or K9F1208U0B-V,F CE must be held low during tRtRData Output(Sequential)Spare Field A0 ~ A7 & A9 ~ A25Main array Data FieldSpare FieldFigure 9. Sequential Row Read1 Operation (only for K9F1208X0B-Y,P and K9F1208X0B-V,F valid within a block) R/BI/OX00h01hStart Add.(4Cycle)A0 ~ A7 & A9 ~ A25( 00h Command)1st half array 2nd half arraytRtRtRData Output1stData Output2nd(528 Byte)( 01h Command)1st half array 2nd half array≈Data OutputNth(528 Byte)Block1st2ndNth1st2ndNth Data FieldSpare Field Data FieldSpare FieldThe Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read-out, the sequential read operation must be terminated by bringing CE high. When the page address moves ontothe next block, read command and address must be given.33K9F1208R0BK9F1208B0BK9F1208U0B

PreliminaryFLASH MEMORY

Figure 10. Sequential Row Read2 Operation (only for K9F1208U0B-Y,P and K9F1208U0B-V,F valid within a block)

R/BI/OX

50h

Start Add.(4Cycle)A0 ~ A3 & A9 ~ A25(A4 ~ A7 : Don’t Care)

≈tR

Data Output

1st

Data Output

2nd(16Byte)

Data OutputNth(16Byte)

1st

Block Nth

Data FieldSpare FieldPAGE PROGRAM

The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytesup to 528 bytes, in a single page program cycle. The number of consecutive partial page programming operation within the samepage without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done inany random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may beloaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropri-ate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to theattached technical notes.

The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input andthen serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-gramming process. The internal write state control automatically executes the algorithms and timings necessary for program andverify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register commandmay be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycleby monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command arevalid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11).The internal write verify detects only errors for \"1\"s that are not successfully programmed to \"0\"s. The command register remains inRead Status command mode until another valid command is written to the command register.

Figure 11. Program & Read Status Operation

R/BI/O0~7

80h

Address & Data InputA0 ~ A7 & A9 ~ A25528 Byte Data

tPROG

10h70hI/O0Pass

Fail

K9F1208R0BK9F1208B0BK9F1208U0B

BLOCK ERASE

PreliminaryFLASH MEMORY

The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an EraseSetup command(60h). Only address A14 to A25 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following theblock address loading initiates the internal erasing process. This two-step sequence of setup followed by execution commandensures that memory contents are not accidentally erased due to external noise conditions.

At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. Whenthe erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.

Figure 12. Block Erase Operation

R/BI/OX

60h

tBERS

Address Input(3Cycle)Block Add. : A14 ~ A25

D0h

70hI/O0Pass

Fail

Multi-Plane Page Program

Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Sincethe device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous program-ming of four pages. Partial activation of four planes is also permitted.

After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead ofactual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programmingprocess is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next setof data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming pro-cess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmedsimultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to \"1\" when any of the pagesfails. Multi-Plane page Program with \"01h\" pointer is not supported, thus prohibited.

Figure 13. Four-Plane Page Program

R/BI/OX

80h

tDBSYtDBSYtDBSYtPROG

528 bytes

Address &11h Data InputA0 ~ A7 & A9 ~ A25

80h

Address & Data Input

11h

80h

Address & Data Input

11h80h

Address & Data Input

10h71h

DataInput

80h11h80h11h

80h11h80h10h

Plane 0

(1024 Block)Plane 1

(1024 Block)Plane 2

(1024 Block)Plane 3

(1024 Block)

Block 0Block 4

Block 1Block 5

Block 2Block 6

Block 3Block 7

Block 4088Block 4092

Block 40Block 4093Block 4090Block 4094

Block 4091Block 4095

K9F1208R0BK9F1208B0BK9F1208U0B

Restriction in addressing with Multi Plane Page Program

PreliminaryFLASH MEMORY

While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for theselected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block isselected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15.

Figure 14. Multi-Plane Program & Read Status Operation

Plane 0

(1024 Block)

Plane 1

(1024 Block)

Plane 2

(1024 Block)

Plane 3

(1024 Block)

Block 0

Page 0Page 1

Block 1

Page 0Page 1

Block 2

Page 0Page 1

Block 3

Page 0Page 1

Page 30Page 31Page 30Page 31Page 30Page 31Page 30Page 31

Figure 15. Addressing Multiple Planes

80h Plane 211h80h

Plane 0

11h80h

Plane3

11h80h

Plane 1

10h

Figure 16. Multi-Plane Page Program & Read Status Operation

R/BI/O0~7

80h

tPROG

Last Plane input

Address & Data InputA0 ~ A7 & A9 ~ A25

I/O

Pass

10h71h

528 bytes

Fail

Multi-Plane Block Erase

Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from eachplane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by threeaddress cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane.The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busystatus (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1through I/O 4).

Figure 17. Four Block Erase Operation

R/BI/OX

60h

Address (3 Cycle)

60h

Address (3 Cycle)

60h

Address (3 Cycle)

60h

Address (3 Cycle)

D0h

tBERS

71h

I/O

Pass

A0 ~ A7 & A9 ~ A25

Fail36

K9F1208R0BK9F1208B0BK9F1208U0B

Copy-Back Program

PreliminaryFLASH MEMORY

The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are

removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read opera-tion with \"00h\" command and the address of the source page moves the whole 528byte data into the internal page registers. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page pro-gramming into the copied pages is prohibited before erase. A14 and A15 must be the same between source and target page.

Figure18 shows the command sequence for single plane operation. \"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. For this reason, two bit ECC is recommended for copy-back operation.\"

Figure 18. One Page Copy-Back program Operation

R/BI/OX

00h

Add.(4Cycles) A0 ~ A7 & A9 ~ A25Source Address

tRtPROG

8AhAdd.(4Cycles) A0 ~ A7 & A9 ~ A25Destination Address10h70hI/O0Pass

Fail

K9F1208R0BK9F1208B0BK9F1208U0B

Multi-Plane Copy-Back Program

PreliminaryFLASH MEMORY

Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device isequipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane Copy-Back programming of four pages. Partial activation of four planes is also permitted.

First, normal read operation with the \"00h\"command and address of the source page moves the whole 528 byte data into internalpage buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executedwith \"03h\" command instead of \"00h\" command. Any plane may be selected without regard to \"00h\" or \"03h\". Up to four planes maybe addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of com-mand sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacementaddress command with \"8Ah\" is executed. Since no programming process is involved during data loading at the destination planeaddress , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may beissued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the lastplane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programmingprocess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmedsimultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supportedwith Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page pro-gramming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished.

Figure 19. Four-Plane Copy-Back Program

Max Three Times Repeatable

SourceAddressInput

00h03h

03h03h

Plane 0

(1024 Block)Plane 1

(1024 Block)Plane 2

(1024 Block)Plane 3

(1024 Block)

Block 0Block 4Block 1Block 5

Block 2Block 6

Block 3Block 7

Block 4088Block 4092

Block 40Block 4093Block 4090Block 4094

Block 4091Block 4095

Max Three Times Repeatable

DestinationAddressInput

8Ah11h8Ah11h

8Ah11h8Ah10h

Plane 0

(1024 Block)Plane 1

(1024 Block)Plane 2

(1024 Block)Plane 3

(1024 Block)

Block 0Block 4

Block 1Block 5

Block 2Block 6

Block 3Block 7

Block 4088Block 4092

Block 40Block 4093Block 4090Block 4094

Block 4091Block 4095

K9F1208R0BK9F1208B0BK9F1208U0B

Figure 20. Four-Plane Copy-Back Page Program (Continued)≈≈R/B≈≈I/OX03h8Ah Add.(4Cyc.)11h11h8Ah Add.(4Cyc.)A0 ~ A7 & A9 ~ A25Destination AddressA0 ~ A7 & A9 ~ A25Destination Address Add.( 4Cyc.) A0 ~ A7 & A9 ~ A25Source Address8Ah Add.(4Cyc.)≈00h Add.(4Cyc.) 03h≈tRtDBSYtDBSYtRtRtPROG10h71hA0 ~ A7 & A9 ~ A25Source Address Add.( 4Cyc.) A0 ~ A7 & A9 ~ A25Source AddressA0 ~ A7 & A9 ~ A25Destination AddresstR : Normal Read BusyMax. 4 times (4 Cycle Destination Address Input) repeatabletDBSY : Typical 1us, Max 10usMax. 4 times ( 4 Cycle Source Address Input) repeatable39

PreliminaryFLASH MEMORY

K9F1208R0BK9F1208B0BK9F1208U0B

READ STATUS

PreliminaryFLASH MEMORY

The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whetherthe program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputsthe content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allowsthe system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CEdoes not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command registerremains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random readcycle, a read command(00h or 50h) should be given before sequential page read cycle.

For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/failstatus data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation.

Table4. Read Staus Register Definition

I/O No.I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7

StatusTotal Pass/FailPlane 0 Pass/FailPlane 1 Pass/FailPlane 2 Pass/FailPlane 3 Pass/Fail

ReservedDevice OperationWrite Protect

Definition by 70h CommandPass : \"0\" Fail : \"1\"Must be don’t -caredMust be don’t -caredMust be don’t -caredMust be don’t -caredMust be don’t -cared

Busy : \"0\" Ready : \"1\"Protected : \"0\" Not Protected : \"1\"

Definition by 71h CommandPass : \"0\"(1) Fail : \"1\"Pass : \"0\"(2) Fail : \"1\"Pass : \"0\"(2) Fail : \"1\"Pass : \"0\"(2) Fail : \"1\"Pass : \"0\"(2) Fail : \"1\"Must be don’t-cared

Busy : \"0\" Ready : \"1\"Protected : \"0\" Not Protected : \"1\"

NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/

Erase operation, it sets \"Fail\" flag.

2. The pass/fail status applies only to the corresponding plane.

K9F1208R0BK9F1208B0BK9F1208U0BRead IDPreliminaryFLASH MEMORYThe device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of00h. Four read cycles sequentially output the manufacture code(ECh), and the device code, Reserved(A5h), Multi plane operationcode(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation but must be don’t-cared for1.8V device. The command register remains in Read ID mode until further commands are issued to it. Figure 21 shows the operationsequence.Figure 21. Read ID Operation 1CLEtCEACEWEtARALEREI/O0~790htWHR00hAddress. 1cycletREAEChMaker codeDeviceCodeDevice codeA5hC0hMulti-Plane code DeviceK9F1208R0BK9F1208B0BK9F1208U0BDevice Code36h76h76h41K9F1208R0BK9F1208B0BK9F1208U0B

RESET

PreliminaryFLASH MEMORY

The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during randomread, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are nolonger valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, andthe Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device isalready in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRSTafter the Reset command is written. Refer to Figure 22 below.

Figure 22. RESET Operation

R/BI/O0~7

FFh

tRST

Table5. Device Status

After Power-up

Operation Mode

After Reset

Waiting for next command

K9F1208R0BK9F1208B0BK9F1208U0B

READY/BUSY

PreliminaryFLASH MEMORY

The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and randomread . The R/B pin is normally high but transitions to low after program or erase command is written to the command register or ran-dom read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and currentdrain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 23). Its value can be deter-mined by the following guidance.

VCC

ibusy

1.8V device - VOL : 0.1V, VOH : VccQ-0.1V2.7V device - VOL : 0.4V, VOH : VccQ-0.4V3.3V device - VOL : 0.4V, VOH : 2.4V

Ready Vcc

R/B

open drain outputVOH

CL VOL

Busy

GND

Device

Figure 23. Rp vs tr ,tf & Rp vs ibusy

K9F1208R0BK9F1208B0BK9F1208U0B@ Vcc = 1.8V, Ta = 25°C , CL = 30pFPreliminaryFLASH MEMORYtr,tf [s]300n1.7Ibusy3mIbusy [A]Ibusy [A]200n100n2mtr0.8560900.571.7120301.70.431.71mtf1.71K2K3KRp(ohm)4K@ Vcc = 2.7V, Ta = 25°C , CL = 30pFtr,tf [s]300nIbusy1.1200n100n302.32m900.752.3120trtf602.31m2.30.551K2K3KRp(ohm)4K@ Vcc = 3.3V, Ta = 25°C , CL = 100pF2.4400tr,tf [s]300nIbusy1.22003003m200ntr100n1003.6tf0.80.62m1m3.63.63.61K2KRp value guidanceRp(min, 1.8V part) =VCC(Max.) - VOL(Max.) IOL + ΣILRp(min, 2.7V part) =VCC(Max.) - VOL(Max.) IOL + ΣILRp(min, 3.3V part) =VCC(Max.) - VOL(Max.) IOL + ΣIL3KRp(ohm)4K1.85V =3mA + ΣIL2.4V =3mA + ΣIL3.2V =8mA + ΣILwhere IL is the sum of the input currents of all devices tied to the R/B pin.Rp(max) is determined by maximum permissible limit of tr 44Ibusy [A]2.33mK9F1208R0BK9F1208B0BK9F1208U0B

Data Protection & Power-up sequence

PreliminaryFLASH MEMORY

The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detectordisables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hard-ware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs isrequired before internal circuit gets ready for any command sequences as shown in Figure 24. The two step command sequence forprogram/erase provides additional software protection.

Figure 24. AC Waveforms for Power Transition

1.8V device : ~ 1.5V2.7V device : ~ 2.0V3.3V device : ~ 2.4V

VCC

High

1.8V device : ~ 1.5V2.7V device : ~ 2.0V3.3V device : ~ 2.4V

≈10µs

≈≈≈

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