Stacked integrated circuit and capacitor structure

专利名称：Stacked integrated circuit and capacitor

structure containing via structures

发明人：Matthew S. Buynoski申请号：US094882申请日：20000120公开号：US052250B1公开日：20020917

专利附图：

摘要：An integrated circuit structure includes a planar capacitor positioned adjacentto a logic circuit implemented on a silicon die. The silicon die is bonded to a mountingbase using controlled collapse chip connection methods such that a ground terminal of

the silicon die is coupled to a ground trace in the mounting base and a Vdd terminal ofthe silicon die is coupled to a Vdd trace in the mounting base. The capacitor includes viastructures with controlled collapse chip connection structures for bonding to themounting base directly above the silicon die and coupling a first charge accumulationplate to the Vdd trace and a second charge accumulation plate to the ground trace.

申请人：ADVANCED MICRO DEVICES, INC.

代理机构：Renner, Otto, Boisselle & Sklar, LLP

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