M4A5-32-32-10

High Performance E2CMOS® In-System Programmable Logic

FEATURES

xHigh-performance, E2CMOS 3.3-V & 5-V CPLD familiesxFlexible architecture for rapid logic designs

ispMACH™ 4A CPLD Family

x

xxx

x

xx

x

—Excellent First-Time-FitTM and refit feature

—SpeedLockingTM performance for guaranteed fixed timing

—Central, input and output switch matrices for 100% routability and 100% pin-out retentionHigh speed

—5.0ns tPD Commercial and 7.5ns tPD Industrial—182MHz fCNT

32 to 512 macrocells; 32 to 768 registers

44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packagesFlexible architecture for a wide range of design styles—D/T registers and latches

—Synchronous or asynchronous mode—Dedicated input registers—Programmable polarity—Reset/ preset swapping

Advanced capabilities for easy system integration—3.3-V & 5-V JEDEC-compliant operations

—JTAG (IEEE 1149.1) compliant for boundary scan testing—3.3-V & 5-V JTAG in-system programming

—PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)—Safe for mixed supply voltage system designs

—Programmable pull-up or Bus-FriendlyTM inputs and I/Os—Hot-socketing

—Programmable security bit

—Individual output slew rate control

Advanced E2CMOS process provides high-performance, cost-effective solutionsSupported by ispDesignEXPERTTM software for rapid logic development

—Supports HDL design methodologies with results optimized for ispMACH 4A—Flexibility to adapt to user requirements

—Software partnerships that ensure customer successLattice and third-party hardware programming support

—LatticePROTM software for in-system programmability support on PCs and automated test equipment

—Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

Publication# ISPM4AAmendment/0Rev: D

Issue Date: August 2000

Table 1. ispMACH 4A Device Features

3.3 V DevicesFeatureMacrocellsUser I/O optionstPD (ns)fCNT (MHz)tCOS (ns)tSS (ns)Static Power (mA)JTAG CompliantPCI Compliant5 V DevicesFeatureMacrocellsUser I/O optionstPD (ns)fCNT (MHz)tCOS (ns)tSS (ns)Static Power (mA)JTAG CompliantPCI Compliant

M4A5-32232325.01824.03.020YesYes

M4A5-64264325.51674.03.525YesYes

M4A5-96296485.51674.03.540YesYes

M4A5-1282128645.51674.03.555YesYes

M4A5-1921192966.01604.53.574YesYes

M4A5-25622561286.51545.03.5110YesYes

M4A3-32232325.01824.03.020YesYes

M4A3-6426432/6415.51674.03.525/521YesYes

M4A3-96296485.51674.03.540YesYes

M4A3-1282128645.51674.03.555YesYes

M4A3-1922192966.01604.53.585YesYes

M4A3-2562561282/1601/19215.531674.03.51102/1501

YesYes

M4A3-3842384160/1926.51544.53.5149/155YesYes

M4A3-5121512160/192/256

7.51255.55.0179YesYes

Notes:

1.Advance information. Please contact a Lattice sales representative for details on availability.2.Preliminary information.

3.M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192

2ispMACH 4A Family

GENERAL DESCRIPTION

The ispMACH™ 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD

solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.

ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity.

All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Table 2).

Table 2. ispMACH 4A Speed Grades

Speed Grade

DeviceM4A3-323M4A5-323M4A3-64/323M4A5-64/323M4A3-64/642M4A3-963M4A5-963M4A3-1283M4A5-1283M4A3-1923M4A5-1922M4A3-256/1283M4A5-256/1283M4A3-256/1922M4A3-256/1602M4A3-3842M4A3-5122

Notes:

1.C = Commercial, I = Industrial

2.Advance information. Please contact a Lattice sales representative for details on availability.3.Preliminary information.

C

C

C

-5C

CCCC

C

CC

-55

-6

-65

-7C, IC, IC, IC, IC, IC, IC, ICC

-10C, IC, IC, IC, IC, IC, I C, IC, IC, IC, IC, I

-12IIIIIIIIIC, IC, I

II-14

ispMACH 4A Family3

The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/Os, a programmable power-down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition.

Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)

3.3 V Devices

Package44-pin PLCC44-pin TQFP48-pin TQFP100-pin TQFP100-pin PQFP100-ball caBGA144-pin TQFP144-ball fpBGA208-pin PQFP256-ball fpBGA256-ball BGA388-ball fpBGA

5 V Devices

Package44-pin PLCC44-pin TQFP48-pin TQFP100-pin TQFP100-pin PQFP144-pin TQFP208-pin PQFP256-ball BGA

M4A5-32232+232+232+2

M4A5-64232+232+232+2

48+8

64+664+6

96+16

128+14128+14

M4A5-962M4A5-1282M4A5-1921M4A5-2562M4A3-32232+232+232+2

M4A3-6432+2232+2232+2264+61

48+8

64+6264+6264+61

96+16296+161

128+142, 1601128+142, 1921128+142160192192

256160192

M4A3-962M4A3-128

M4A3-192

M4A3-256

M4A3-3841M4A3-5121Note:

1.Advance information. Please contact a Lattice sales representative for details on availability.2.Preliminary information.

4ispMACH 4A Family

FUNCTIONAL DESCRIPTION

The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL® blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices.

The key to being able to make effective use of these devices lies in the interconnect schemes. In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms

through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently.

PAL BlockClockGeneratorClock/InputPinsNote 34Note 2Central Switch MatrixLogicArrayInputSwitchMatrixLogic16Output/AllocatorBuriedwith XORMacrocells16168Note 1DedicatedInput Pins16I/O Cells33/34/36Output Switch MatrixI/OPinsI/OPinsPAL BlockPAL BlockI/OPins17466G-001

Figure 1. ispMACH 4A Block Diagram and PAL Block Structure

Notes:

1.16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).2.Block clocks do not go to I/O cells in M4A(3,5)-32/32.

3.M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do

not connect to the central switch matrix.

ispMACH 4A Family5

Table 4. Architectural Summary of ispMACH 4A devices

ispMACH 4A Devices

M4A3-64/32, M4A5-64/32M4A3-96/48, M4A5-96/48M4A3-128/64, M4A5-128/64M4A3-192/96, M4A5-192/96M4A3-256/128, M4A5-256/128

M4A3-384M4A3-512

Macrocell-I/O Cell Ratio

Input Switch MatrixInput RegistersCentral Switch MatrixOutput Switch Matrix

2:1YesYesYesYes

M4A3-32/32M4A5-32/32M4A3-64/64M4A3-256/160M4A3-256/192

1:1Yes1NoYesYes

The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block (Table 4).

The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate with each other with consistent, predictable delays. The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device.Each PAL block consists of:

xxxxxxx

Product-term arrayLogic allocatorMacrocells

Output switch matrixI/O cells

Input switch matrixClock generator

Notes:

1.M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.

6ispMACH 4A Family

Product-Term Array

The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided in both true and complement forms for efficient logic implementation.

Table 5. PAL Block Inputs

Device

M4A3-32/32 and M4A5-32/32M4A3-64/32 and M4A5-64/32M4A3-64/64

M4A3-96/48 and M4A5-96/48M4A3-128/64 and M4A5-128/64M4A3-192/96 and M4A5-192/96M4A3-256/128 and M4A5-256/128M4A3-256/160 and M4A3-256/192M4A3-384M4A3-512

Number of Inputs to PAL Block

33333333333434363636

Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in “product term clusters.” The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number of unused—or wasted—product terms left over. The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7.

Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration of the associated macrocell. When the macrocell is used in synchronous mode(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing.In addition, there is an extra product term that can either join the basic cluster to give an

extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18 product terms.

When the extra product term is used to extend the cluster, the value of the second XOR input can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are shown in Figures 3 and 4.

ispMACH 4A Family7

Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)

Output MacrocellM0M1M2M3M4M5M6M7

Available ClustersC0, C1, C2C0, C1, C2, C3C1, C2, C3, C4C2, C3, C4, C5C3, C4, C5, C6C4, C5, C6, C7C5, C6, C7, C8C6, C7, C8, C9

Output MacrocellM8M9M10M11M12M13M14M15

Available ClustersC7, C8, C9, C10C8, C9, C10, C11C9, C10, C11, C12C10, C11, C12, C13C11, C12, C13, C14C12, C13, C14, C15C13, C14, C15C14, C15

Table 7. Logic Allocator for M4A(3,5)-32/32

Output MacrocellM0M1M2M3M4M5M6M7

Available ClustersC0, C1, C2C0, C1, C2, C3C1, C2, C3, C4C2, C3, C4, C5C3, C4, C5, C6C4, C5, C6, C7C5, C6, C7C6, C7

From n-1Output MacrocellM8M9M10M11M12M13M14M15Available ClustersC8, C9, C10C8, C9, C10, C11C9, C10, C11, C12C10, C11, C12, C13C11, C12, C13, C14C12, C13, C14, C15C13, C14, C15C14, C15

To n-1To n-2Logic AllocatorBasic Product Term Clusternn0 DefaultTo n+1From n+1From n+2ExtraProductTerm0 DefaultProg. PolarityTo Macrocelln17466G-005

a. Synchronous ModeFrom n-1To n-1To n-2Logic AllocatorBasic Product Term Clusternn0 DefaultExtraProductTermFrom n+1From n+2To n+10 DefaultProg. Polarityb. Asynchronous ModeTo Macrocelln17466G-006

Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”

8ispMACH 4A Family

a. Basic cluster with XORb. Extended cluster, active highc. Extended cluster, active low0d. Basic cluster routed away;single-product-term, active high

e. Extended cluster routed away

17466G-007

Figure 3. Logic Allocator Configurations: Synchronous Mode

a. Basic cluster with XORb. Extended cluster, active highc. Extended cluster, active low0d. Basic cluster routed away;single-product-term, active high

e. Extended cluster routed away

17466G-008

Figure 4. Logic Allocator Configurations: Asynchronous Mode

Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All configurations have the same delay. This means that designers do not have to decide between optimizing resources or speed; both can be optimized.

If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell.

Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available.

ispMACH 4A Family9

Macrocell

The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and

asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell.

Power-UpResetPAL-BlockInitializationProduct TermsCommon PAL-block resourceIndividual macrocell resourcesSWAPTo Output and InputSwitch MatricesFrom Logic AllocatorFrom PAL-ClockGeneratorBlock CLK0Block CLK1Block CLK2Block CLK3APD/T/LARQ17466G-009a. Synchronous mode

Power-UpResetIndividualInitializationProduct TermFrom LogicAllocator From PAL-BlockClock GeneratorIndividual ClockProduct TermBlock CLK0Block CLK1APARQD/T/LTo Output and InputSwitch Matricesb. Asynchronous mode

17466G-010

Figure 5. Macrocell

In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator.

10ispMACH 4A Family

The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be

synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH.

APARDQAPARDQa. D-type with XORb. D-type with programmable D polarityAPARLQAPARLQGGc. Latch with XORd. Latch with programmable D polarityAPARTQf. Combinatorial with XORe. T-type with programmable T polarityg. Combinatorial with programmable polarity

17466G-011

Figure 6. Primary Macrocell Configurations

ispMACH 4A Family11

Table 8. Register/Latch Operation

Configuration

D-type Register

Input(s)D=XD=0D=1T=XT=0T=1D=XD=0D=1

CLK/LE 10,1, ↓ (↑)↑ (↓)↑ (↓)0, 1, ↓ (↑)↑ (↓)↑ (↓)1(0)0(1)0(1)

Q+Q01QQQQ01

T-type Register

D-type Latch

Note:

1.Polarity of CLK/LE can be programmed

Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be programmed.

The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode.

The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire PAL block.

Power-UpReset

PAL-BlockInitializationProduct Terms

APD/T/LARQ PAL-BlockInitializationProduct Terms

APD/LARQ Power-UpPreset

a. Power-up reset

17466G-012

b. Power-up preset

17466G-013

Figure 7. Synchronous Mode Initialization Configurations

12ispMACH 4A Family

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset.

Power-UpReset

Individual

Reset

Product Term

Individual

Preset

Product Term

Power-UpPreset

APD/L/TARQAPD/L/TARQa. Reset

17466G-014

b. Preset

17466G-015

Figure 8. Asynchronous Mode Initialization Configurations

Note that the reset/preset swapping selection feature effects power-up reset as well. The

initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired. The input switch matrix can send the signal back to the central switch matrix as feedback.

Table 9. Asynchronous Reset/Preset Operation

AR0011

Note:

1.Transparent latch is unaffected by AR, AP

AP0101

CLK/LE1XXXX

Q+See Table 8

100

ispMACH 4A Family13

Output Switch Matrix

The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout.

In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells; each macrocell has a choice of four I/O cells. The ispMACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells (Figure 9).

M0M1M2M3M4M5macrocellsM6I/O cellMUXM7M8M9M10M11M12M13M14M15Each I/O cell canchoose one of 8macrocells inall ispMACH 4Adevices.Each macrocell can driveone of 4 I/O cells inispMACH 4A devices with2:1 macrocell-I/O cell ratio.I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7M0M1M2M3M4M5M6M7M8M9M10M11M12M13M14M15I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O15M0M1M2M3M4M5M6M7M8M9M10M11M12M13M14M15I/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O15Each macrocell can driveone of 8 I/O cells inispMACH 4A devices with 1:1macrocell-I/O cell ratio exceptM4A(3, 5)-32/32 devices.Each macrocell can driveone of 8 I/O cells inM4A(3, 5)-32/32 devices. Figure 9. ispMACH 4A Output Switch Matrix

Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio

MacrocellM0, M1M2, M3M4, M5M6, M7M8, M9

Routable to I/O CellsI/O0, I/O5, I/O6, I/O7I/O0, I/O1, I/O6, I/O7I/O0, I/O1, I/O2, I/O7I/O0, I/O1, I/O2, I/O3I/O1, I/O2, I/O3, I/O4

14ispMACH 4A Family

Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio

MacrocellM10, M11M12, M13M14, M15I/O CellI/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7

Routable to I/O CellsI/O2, I/O3, I/O4, I/O5I/O3, I/O4, I/O5, I/O6I/O4, I/O5, I/O6, I/O7Available MacrocellsM0, M1, M2, M3, M4, M5, M6, M7M2, M3, M4, M5, M6, M7, M8, M9M4, M5, M6, M7, M8, M9, M10, M11M6, M7, M8, M9, M10, M11, M12, M13M8, M9, M10, M11, M12, M13, M14, M15M0, M1, M10, M11, M12, M13, M14, M15M0, M1, M2, M3, M12, M13, M14, M15M0, M1, M2, M3, M4, M5, M14, M15

Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192

MacrocellM0M1M2M3M4M5M6M7M8M9M10M11M12M13M14M15I/O CellI/O0I/O1I/O2I/O3I/O4I/O5I/O6

M0M0M0M0M0M0M0

M1 M1 M1 M1 M1 M1 M1

M2 M2 M2 M2 M2 M2 M2

M3 M3 M3 M3 M3 M3 M3

I/O0I/O0I/O0I/O0I/O0I/O0I/O0I/O0I/O8I/O8I/O8I/O8I/O8I/O8I/O8I/O8

I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O9 I/O9 I/O9 I/O9 I/O9 I/O9 I/O9 I/O9

I/O2 I/O2 I/O2 I/O2 I/O2 I/O2 I/O2 I/O2 I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 I/O10

I/O3 I/O3 I/O3 I/O3 I/O3 I/O3 I/O3 I/O3 I/O11 I/O11 I/O11 I/O11 I/O11 I/O11 I/O11 I/O11

Routable to I/O CellsI/O4I/O4I/O4I/O4I/O4I/O4I/O4I/O4I/O12I/O12I/O12I/O12I/O12I/O12I/O12I/O12

I/O5I/O5I/O5I/O5I/O5I/O5I/O5I/O5I/O13I/O13I/O13I/O13I/O13I/O13I/O13I/O13

I/O6I/O6I/O6I/O6I/O6I/O6I/O6I/O6I/O14I/O14I/O14I/O14I/O14I/O14I/O14I/O14

I/O7I/O7I/O7I/O7I/O7I/O7I/O7I/O7I/O15I/O15I/O15I/O15I/O15I/O15I/O15I/O15

Available Macrocells M4 M4 M4 M4 M4 M4 M4

M5M5M5M5M5M5M5

M6 M6 M6 M6 M6 M6 M6

M7M7M7M7M7M7M7

ispMACH 4A Family15

Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192

MacrocellI/O7I/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O15

M0M8M8M8M8M8M8M8M8

M1 M9 M9 M9 M9 M9 M9 M9 M9

M2 M10 M10 M10 M10 M10 M10 M10 M10

M3 M11 M11 M11 M11 M11 M11 M11 M11

Routable to I/O Cells M4 M12 M12 M12 M12 M12 M12 M12 M12

M5M13M13M13M13M13M13M13M13

M6 M14 M14 M14 M14 M14 M14 M14 M14

M7M15M15M15M15M15M15M15M15

Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32

Macrocell

M0, M1, M2, M3, M4, M5, M6, M7M8, M9, M10, M11, M12, M13, M14, M15

I/O Cell

I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

Routable to I/O Cells

I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

Available MacrocellsM0, M1, M2, M3, M4, M5, M6, M7M8, M9, M10, M11, M12, M13, M14, M15

Table 13. Output Switch Matrix Combinations for M4A3-64/64

MacrocellMO, M1M2, M3M4, M5M6, M7M8, M9M10, M11M12, M13M14, M15I/O CellI/O0, I/O1I/O2, I/O3I/O4, I/O5I/O6, I/O7I/O8, I/O9I/O10, I/O11I/O12, I/O13I/O14, I/O15

Routable to I/O Cells

I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15

Available MacrocellsM0, M1, M2, M3, M4, M5, M6, M7M2, M3, M4, M5, M6, M7, M8, M9M4, M5, M6, M7, M8, M9, M10, M11M6, M7, M8, M9, M10, M11, M12, M13M8, M9, M10, M11, M12, M13, M14, M15M0, M1, M10, M11, M12, M13, M14, M15M0, M1, M2, M3, M12, M13, M14, M15M0, M1, M2, M3, M4, M5, M14, M15

16ispMACH 4A Family

I/O Cell

The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable product term is provided for each I/O cell. The feedback signal drives the input switch matrix.

IndividualOutput EnableProduct Term From OutputSwitch MatrixIndividualOutput EnableProduct Term From OutputSwitch MatrixToInputSwitchMatrix

QD/LBlock CLK0Block CLK1Block CLK2Block CLK3Power-up reset17466G-017

17466G-018

ToInputSwitchMatrix

Figure 10. I/O Cell for ispMACH 4A Devices with 2:1 Figure 11. I/O Cell for ispMACH 4A Devices with 1:1

Macrocell-I/O Cell RatioMacrocell-I/O Cell Ratio

The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input

in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of the input are sent to the input switch matrix. This allows for such functions as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the second data value is put on the I/O pin and compared with the previous stored value. Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells. It powers up to a logic low.

Zero-Hold-Time Input Register

The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges.

ispMACH 4A Family17

Input Switch Matrix

The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix.

From Input CellFrom Macrocell 1From Macrocell 2DirectRegistered/LatchedTo Central Switch Matrix17466G-002

To Central Switch Matrix Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell

Ratio - Input Switch MatrixRatio - Input Switch Matrix

18ispMACH 4A Family

From Macrocell17466G-003

From I/O PinPAL Block Clock Generation

Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. Table 14 lists the possible combinations.

GCLK0Block CLK0(GCLK0 or GCLK1)Block CLK1(GCLK1 or GCLK0)Block CLK2(GCLK2 or GCLK3)Block CLK3(GCLK3 or GCLK2)17466G-004

GCLK1GCLK2GCLK3 Figure 14. PAL Block Clock Generator 1

1.M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is

tied to GCLK1.

Table 14. PAL Block Clock Combinations1

Block CLK0 GCLK0GCLK1GCLK0GCLK1XXXX

Block CLK1 GCLK1GCLK1GCLK0GCLK0XXXX

Block CLK2 XXXX

GCLK2 (GCLK0)GCLK3 (GCLK1)GCLK2 (GCLK0)GCLK3 (GCLK1) Block CLK3XXXX

GCLK3 (GCLK1)GCLK3 (GCLK1)GCLK2 (GCLK0)GCLK2 (GCLK0)Note:

1.Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.

This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration.

ispMACH 4A Family19

ispMACH 4A TIMING MODEL

The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH 4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction

between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback.The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized ispMACH 4A timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed discussion about the timing parameters.

(External Feedback)(Internal Feedback)COMB/DFF/TFF/LATCH/SR*/JK*INCentralSwitchMatrix*emulatedtSLWtBUFOUTtPLINPUT REG/INPUT LATCHtSIRS tHIRStSILtHILtSIRZtHIRZtSILZtHILZBLK CLKtPDILi tICOSi tIGOSi tPDILZiQtSS(T)tSA(T)tH(S/A)tS(S/A)LtH(S/A)LtSRRtPDi QtPDLi tCO(S/A)itGO(S/A)itSRiS/RtEAtER 17466G-025

Figure 15. ispMACH 4A Timing Model

SPEEDLOCKING FOR GUARANTEED FIXED TIMING

The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an XOR gate without incurring additional timing delays.The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is

independent of the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs easy access to the performance required in today’s designs.

20ispMACH 4A Family

IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY

All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing.

IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of significant benefits including: rapid

prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 4A devices provide In-System Programming (ISP) capability through their

Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the

communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface.

ispMACH 4A devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of ispMACH 4A devices. LatticePRO takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equpment can then be used to program ispMACH 4A devices during the testing of a circuit board.

PCI COMPLIANT

ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature.

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS

Both the 3.3-V and 5-V VCC ispMACH 4A devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixed-voltage design capability.

PULL UP OR BUS-FRIENDLY INPUTS AND I/Os

All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry

incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

ispMACH 4A Family

21

All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

POWER MANAGEMENT

Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode.

PROGRAMMABLE SLEW RATE

Each ispMACH 4A device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power.

POWER-UP RESET/SET

All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed.

SECURITY BIT

A programmable security bit is provided on the ispMACH 4A devices as a deterrent to

unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.

HOT SOCKETING

ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH devices be minimal on active signals.

22ispMACH 4A Family

CLK0CLK1CLK2CLK3ACLOCKGENERATOR40M4A(3, 5)-64/32M4A3-64/64M4A(3, 5)-96/48M4A(3, 5)-128/64AB1617M4(3, 5)-192/96M4(3, 5)-256/1281717M4A3-384M4A3-5121818C0M0M0M1MACROCELLM1O0MACROCELLI/OCELLI/O0C1C2M2M2M3MACROCELLM3O1MACROCELLI/OCELLI/O1C3C4C5M4M4M5MACROCELLM5MACROCELLO2I/OCELLI/O2C6CENTRAL SWITCH MATRIXLOGIC ALLOCATOROUTPUT SWITCH MATRIXM6M7MACROCELLMACROCELLM6M7O3I/OCELLI/O3C7C8M8M9MACROCELLMACROCELLM8M9O4C9I/OCELLI/O4C10M10M11MACROCELLMACROCELLM10M11O5I/OCELLI/O5C11C12C13M12M13MACROCELLMACROCELLM12M13O6I/OCELLI/O6C14C1589B24M14M15MACROCELLMACROCELLM14M15O7I/OCELLI/O716INPUT SWITCHMATRIX16 Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio

ispMACH 4A Family23

CLK0CLK1CLK2CLK3M4A3-64/64AB1617M4A3-256/160M4A3-256/1921818ACLOCKGENERATOR04M0C0M0M1MACROCELLM1MACROCELLC1O0I/OCELLI/OCELLI/O0I/O1O1C2M2M2M3MACROCELLM3MACROCELLO2O3I/OCELLI/OCELLI/O2I/O3C3C4C5M4M4M5MACROCELLM5MACROCELLO4I/OCELLI/OCELLI/O4I/O5O5CENTRAL SWITCH MATRIXLOGIC ALLOCATORM7M7MACROCELLOUTPUT SWITCH MATRIXC6M6MACROCELLM6O6I/OCELLI/OCELLI/O6C7I/O7O7C8M8M9MACROCELLMACROCELLM8M9O8I/OCELLI/OCELLI/O8C9I/O9O9C10M10MACROCELLMACROCELLM10M11O10I/OCELLI/OCELLI/O10I/O11C11M11O11C12M12MACROCELLMACROCELLM12M13O12I/OCELLI/OCELLI/O12C13M13I/O13O13C14M14MACROCELLMACROCELLM14O14M15O15I/OCELLI/OCELLI/O14C15M1597B1632INPUTSWITCHMATRIXI/O151617466H-41 Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)

24ispMACH 4A Family

CLK0/I016CLK0/I1CLOCKGENERATOR20M0C0M0M1MACROCELLM1MACROCELLC1O0I/OCELLI/OCELLI/O0I/O1O1C2M2M3OUTPUT SWITCH MATRIXM2M3MACROCELLMACROCELLO2O3I/OCELLI/OCELLI/O2I/O3C3C4C5M4M4M5MACROCELLM5MACROCELLO4I/OCELLI/OCELLI/O4I/O5O5CENTRAL SWITCH MATRIXC6LOGIC ALLOCATORM6M7MACROCELLMACROCELLM6O6M7O7I/OCELLI/OCELLI/O6C7I/O7C8M8M9MACROCELLMACROCELLM8M9O8I/OCELLI/OCELLI/O8C9I/O9O9C10M11C11M11MACROCELLOUTPUT SWITCH MATRIXM10MACROCELLM10O10I/OCELLI/OCELLI/O10I/O11O11C12M12MACROCELLMACROCELLM12M13O12I/OCELLI/OCELLI/O12C13M13I/O13O13C14M14MACROCELLMACROCELLM14O14M15O15I/OCELLI/OCELLI/O14C15M1597171632INPUTSWITCHMATRIXI/O1516 Figure 18. PAL Block for M4A (3,5)-32/32

17466H-042

ispMACH 4A Family25

BLOCK DIAGRAM – M4A(3,5)-32/32

Block AI/O8–I/O15I/O0–I/O78I/O CellsClock Generator8Output SwitchMatrix8MacrocellsOEOE8Input SwitchMatrix2848I/O Cells884Output SwitchMatrix8Macrocells8Input SwitchMatrix1616Input SwitchMatrix8MacrocellsClock Generator484888Output SwitchMatrix8I/O Cells88I/O24–I/O31888866 X 98AND Logic Arrayand Logic Allocator33CLK0/I0, CLK1/I1 162Central Switch Matrix216Input SwitchMatrix3366 X 98AND Logic Arrayand Logic AllocatorOEOE8Macrocells88Output SwitchMatrix8I/O Cells828I/O16–I/O23Block B17466H-019

26ispMACH 4A Family

BLOCK DIAGRAM – M4A(3,5)-64/32

Block AI/O0–I/O7Block DI/O24–I/O318I/O CellsClock GeneratorClock Generator4848Output SwitchMatrix16MacrocellsOEOE16Input SwitchMatrix66 X 90AND Logic Arrayand Logic Allocator24848I/O Cells8Output SwitchMatrix16Macrocells1666 X 90AND Logic Arrayand Logic AllocatorInput SwitchMatrix2424Input SwitchMatrix161684Output SwitchMatrix8I/O Cells816161616162CLK0/I0, CLK1/I1 3324332Central Switch Matrix23366 X 90AND Logic Arrayand Logic AllocatorOE16MacrocellsClock GeneratorClock Generator4841616Output SwitchMatrix8I/O Cells816424Input SwitchMatrix3366 X 90AND Logic Arrayand Logic AllocatorOE16Macrocells22I/O8–I/O15I/O16–I/O23Block BBlock C17466H-020

ispMACH 4A Family27

BLOCK DIAGRAM – M4A3-64/64

Block ABlock D16I/O CellsClock GeneratorClock Generator16164Output SwitchMatrix16MacrocellsOEOE1666 X 90AND Logic Arrayand Logic Allocator416I/O Cells16164Output SwitchMatrix16Macrocells1666 X 90AND Logic Arrayand Logic Allocator161616164CLK0/I0, CLK1/I1CLK2/I3, CLK3/I4 33334Central Switch Matrix43366 X 90AND Logic Arrayand Logic AllocatorOE16MacrocellsClock GeneratorClock Generator4161616Output SwitchMatrix16I/O Cells16164163366 X 90AND Logic Arrayand Logic AllocatorOE16Macrocells1616Output SwitchMatrix16I/O Cells1616244Block BBlock C17466H-020A

28ispMACH 4A Family

Block CI/O16–I/O23I/O8–I/O15I/O0–I/O7Block BBlock A8I/O Cells48161616Macrocells16OEMacrocellsOE16Input SwitchMatrix66 X 90AND Logic Arrayand Logic Allocator42466 X 90AND Logic Arrayand Logic Allocator4161641616164MacrocellsOE16Input SwitchMatrix66 X 90AND Logic Arrayand Logic Allocator4243316Output SwitchMatrix88Output SwitchMatrixOutput SwitchMatrixClock Generator8Clock Generator4848I/O CellsI/O Cells88BLOCK DIAGRAM – M4A(3,5)-96/48

333324Input SwitchMatrix4Clock GeneratorI2, I3, I6, I7433243324Central Switch Matrix3324CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5ispMACH 4A Family

Input SwitchMatrixInput SwitchMatrix66 X 90AND Logic Arrayand Logic Allocator4OEOE1616Macrocells16168Output SwitchMatrix8I/O Cells84416841616Output SwitchMatrix8I/O Cells816484Macrocells466 X 90AND Logic Arrayand Logic Allocator4OE1616Clock GeneratorClock Generator88I/O24–I/O31I/O32–I/O3944Input SwitchMatrix466 X 90AND Logic Arrayand Logic AllocatorMacrocells1616Output SwitchMatrixClock GeneratorI/O Cells17466G-021I/O40–I/O4729

Block DBlock EBlock FBlock DI/O24–I/031I/O16–I/O23I/O8–I/O15I/O0–I/O7Block CBlock BBlock A88I/O Cells48416MacrocellsOE16Input SwitchMatrix66 X 90AND Logic Arrayand Logic AllocatorOutput SwitchMatrix8I/O Cells8481616Macrocells16OE41616164MacrocellsOE16Input SwitchMatrixInput SwitchMatrix66 X 90AND Logic Arrayand Logic Allocator4424332466 X 90AND Logic Arrayand Logic Allocator16Output SwitchMatrix8Output SwitchMatrix4Output SwitchMatrix161616Macrocells16Input SwitchMatrix488I/O CellsI/O Cells8844BLOCK DIAGRAM – M4A(3,5)-128/64

Clock GeneratorClock GeneratorClock Generator16163324333324Clock Generator84OE66 X 90AND Logic Arrayand Logic AllocatorI2, I543324332433Central Switch Matrix243324CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4ispMACH 4A Family

Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix4OEOE66 X 90AND Logic Arrayand Logic Allocator416Macrocells1616Output SwitchMatrix88I/O Cells8I/O Cells84168Output SwitchMatrix164161648466 X 90AND Logic Arrayand Logic Allocator16Macrocells1616Output SwitchMatrix8I/O Cells816416MacrocellsClock GeneratorClock GeneratorI/O32–I/O39Block EI/O40–I/O47Block FI/O48–I/O55Block G42Input SwitchMatrix466 X 90AND Logic Arrayand Logic Allocator66 X 90AND Logic Arrayand Logic AllocatorOE16Macrocells4844Clock GeneratorClock Generator4OE1616Output SwitchMatrix8I/O Cells8168I/O56–I/O63Block H17466H-022

30

BLOCK DIAGRAM – M4A(3,5)-192/96

Block BI/O8–I/O15Block AI/O0–I/O7Block LI/O88–I/O95Block KI/O80–I/O87CLK0–CLK3 8 84 4 8 8I/O CellsClock Generator8 4 84 I/O Cells8 I/O CellsClock GeneratorClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 Input SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic Allocator 34 468 X 90AND Logic Arrayand Logic Allocator 34 44 68 X 90AND Logic Arrayand Logic Allocator34 Input SwitchMatrix4 68 X 90AND Logic Arrayand Logic Allocator34 24 2424 24 Input SwitchMatrixBlock C I/O16–I/O23Block D I/O24–I/O31 8 8 8 8I/O72–I/O79 Block JI/O64–I/O71 Block I I/O CellsClock Generator8 4 84 I/O CellsI/O CellsI/O CellsClock Generator 48 48 Central Switch Matrix8 Clock GeneratorClock Generator4 84 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsOE16 MacrocellsOE16 MacrocellsOE16 MacrocellsOE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic Allocator 34 468 X 90AND Logic Arrayand Logic Allocator 34 44 68 X 90AND Logic Arrayand Logic Allocator34 4 68 X 90AND Logic Arrayand Logic Allocator34 24 2424 24 24 34 24 3434 24 34 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic AllocatorOE 16 468 X 90AND Logic Arrayand Logic AllocatorOE 16 44 OE68 X 90AND Logic Arrayand Logic Allocator16 4 OE68 X 90AND Logic Arrayand Logic Allocator16 16 16Macrocells 1616Macrocells4 84 MacrocellsClock GeneratorClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 Clock Generator4 84 16 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O Cells8 16 I/O Cells 8I/O Cells 8I/O32–I/O39Block EI/O40–I/O47Block FI0–I15I/O48–I/O55Block GI/O56–I/O63Block HInput SwitchMatrixInput SwitchMatrix17466G-067

ispMACH 4A Family31

BLOCK DIAGRAM – M4A(3,5)-256/128

Block BI/O8–I/O15Block AI/O0–I/O7CLK0–CLK3Block PI/O120–I/O127Block OI/O112–I/O119 8 84 4 8 8I/O CellsClock Generator8 4 84 I/O Cells8 I/O CellsClock GeneratorClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic Allocator 34 468 X 90AND Logic Arrayand Logic Allocator 34 44 68 X 90AND Logic Arrayand Logic Allocator34 4 68 X 90AND Logic Arrayand Logic Allocator34 24 2424 24 24 34 24 3434 24 34 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic AllocatorOE 16 468 X 90AND Logic Arrayand Logic AllocatorOE 16 44 OE68 X 90AND Logic Arrayand Logic Allocator16 4 OE68 X 90AND Logic Arrayand Logic Allocator16 16 16MacrocellsClock Generator 164 84 16 16Macrocells4 84 MacrocellsClock GeneratorClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O CellsI/O CellsI/O Cells 8Block C I/O16–I/O23Block D I/O24–I/O31Block E I/O32–I/O39Block F I/O40–I/O47 88 Central Switch Matrix 8Input SwitchMatrixInput SwitchMatrix 8 8 8I/O104–I/O111 Block NI/O96–I/O103 Block MI/O88–I/O95 Block LI/O80–I/O87 Block K I/O CellsClock Generator8 4 84 I/O CellsClock Generator8 I/O CellsClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic Allocator 34 468 X 90AND Logic Arrayand Logic Allocator 34 44 68 X 90AND Logic Arrayand Logic Allocator34 4 68 X 90AND Logic Arrayand Logic Allocator34 24 2424 24 24 34 24 3434 24 34 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix68 X 90AND Logic Arrayand Logic AllocatorOE 16 468 X 90AND Logic Arrayand Logic AllocatorOE 16 44 OE68 X 90AND Logic Arrayand Logic Allocator16 4 OE68 X 90AND Logic Arrayand Logic Allocator16 16 16Macrocells 1616Macrocells4 84 MacrocellsClock GeneratorClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 Clock Generator4 84 16 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O Cells8 14 I/O Cells 8I/O Cells 8Input SwitchMatrixInput SwitchMatrixI/O48–I/O55Block GI/O56–I/O63Block HI0–I13I/O64–I/O71Block II/O72–I/O79Block J17466G-02432ispMACH 4A Family

BLOCK DIAGRAM – M4A3-256/160, M4A3-256/192

Block BBlock ACLK0–CLK3Block PBlock O 4 16 16 16 164 I/O CellsI/O CellsI/O CellsI/O CellsClock Generator16 4 164 16 Clock GeneratorClock Generator4 164 416 416 Clock Generator 416 416 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsMacrocellsMacrocellsMacrocellsOEOEOE16 16 16 OE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 98AND Logic Arrayand Logic Allocator 36 472 X 98AND Logic Arrayand Logic Allocator 36 44 72 X 98AND Logic Arrayand Logic Allocator36 4 72 X 98AND Logic Arrayand Logic Allocator36 32 3232 32 32 36 32 3636 32 36 32 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 98AND Logic Arrayand Logic Allocator 472 X 98AND Logic Arrayand Logic Allocator 44 72 X 98AND Logic Arrayand Logic Allocator4 72 X 98AND Logic Arrayand Logic AllocatorOEOEOE 16 1616 OE16 16 16Macrocells16Macrocells4 164 Macrocells16Macrocells1616 Clock Generator4 164 Clock GeneratorClock Generator 16 16 16 416 416 Clock Generator 416 416 Output SwitchMatrix 16Output SwitchMatrix 16Output SwitchMatrix16 16 Output SwitchMatrix16 I/O Cells16 I/O CellsI/O CellsI/O Cells 16Block CBlock DBlock EBlock F 1616 Central Switch Matrix 16Input SwitchMatrixInput SwitchMatrix 16 16 16Block NBlock MBlock LBlock K I/O CellsI/O CellsI/O CellsI/O CellsClock GeneratorClock Generator16 4 164 16 Clock Generator4 164 416 416 Clock Generator 416 416 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsMacrocellsMacrocellsMacrocellsOEOEOE16 16 16 OE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 98AND Logic Arrayand Logic Allocator 36 472 X 98AND Logic Arrayand Logic Allocator 36 44 72 X 98AND Logic Arrayand Logic Allocator36 4 72 X 98AND Logic Arrayand Logic Allocator36 32 3232 32 32 36 32 3636 32 36 32 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 98AND Logic Arrayand Logic Allocator 472 X 98AND Logic Arrayand Logic Allocator 44 72 X 98AND Logic Arrayand Logic Allocator4 72 X 98AND Logic Arrayand Logic AllocatorOEOEOE 16 1616 OE16 16 16Macrocells 1616Macrocells4 164 Macrocells16Macrocells1616 Clock Generator4 164 Clock Generator 16 16Clock Generator 416 416 Clock Generator 416 416 Output SwitchMatrix 16Output SwitchMatrix 16Output SwitchMatrix16 16 Output SwitchMatrix16 I/O Cells16 I/O Cells16 I/O Cells 16I/O Cells 16Block GBlock HBlock IBlock JispMACH 4A Family

Input SwitchMatrixInput SwitchMatrix17466G-050

33

BLOCK DIAGRAM – M4A3-384/160, M4A3-384/192

CLK0–CLK3Block BBlock A 4Block HXBlock GXDetail A 8 84 4 8 8I/O CellsClock Generator8 4 84 I/O Cells8 I/O CellsClock GeneratorClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic Allocator 36 472 X 90AND Logic Arrayand Logic Allocator 36 44 72 X 90AND Logic Arrayand Logic Allocator36 4 72 X 90AND Logic Arrayand Logic Allocator36 24 2424 24 24 36 24 3636 24 36 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic AllocatorOE 16 472 X 90AND Logic Arrayand Logic AllocatorOE 16 44 72 X 90AND Logic Arrayand Logic AllocatorOE16 4 OE72 X 90AND Logic Arrayand Logic Allocator16 Central Switch Matrix16 16MacrocellsClock Generator 164 84 16 16Macrocells4 84 MacrocellsClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 Clock Generator 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O Cells8 I/O Cells 8I/O Cells 8Block CBlock FBlock DBlock EBlock EXBlock DXRepeat Detail ABlock GBlock JBlock HBlock IBlock AXBlock PBlock BXBlock O 8 8 8 8I/O CellsClock Generator8 4 84 I/O Cells8 I/O CellsClock GeneratorClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 16Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic Allocator 36 472 X 90AND Logic Arrayand Logic Allocator 36 44 72 X 90AND Logic Arrayand Logic Allocator36 4 72 X 90AND Logic Arrayand Logic Allocator36 24 2424 24 24 36 24 3636 24 36 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic AllocatorOE 16 472 X 90AND Logic Arrayand Logic AllocatorOE 16 44 OE72 X 90AND Logic Arrayand Logic Allocator16 4 OE72 X 90AND Logic Arrayand Logic Allocator16 16 16MacrocellsClock Generator 164 84 16 16Macrocells4 84 MacrocellsClock GeneratorClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O Cells8 I/O Cells 8I/O Cells 8Block KBlock LBlock MBlock NInput SwitchMatrixInput SwitchMatrixInput SwitchMatrixBlock FXBlock CX 16 Input SwitchMatrix17466G-067

34ispMACH 4A Family

BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256

CLK0–CLK3Block BBlock A 4Block PXBlock OXDetail A 8 84 4 8 8I/O CellsClock Generator8 4 84 I/O Cells8 I/O CellsClock GeneratorClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 16 16MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic Allocator 36 472 X 90AND Logic Arrayand Logic Allocator 36 44 72 X 90AND Logic Arrayand Logic Allocator36 4 72 X 90AND Logic Arrayand Logic Allocator36 24 2424 24 24 36 24 3636 24 36 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic AllocatorOE 16 472 X 90AND Logic Arrayand Logic AllocatorOE 16 44 72 X 90AND Logic Arrayand Logic AllocatorOE16 4 OE72 X 90AND Logic Arrayand Logic Allocator16 Central Switch Matrix16 16MacrocellsClock Generator 164 84 16 16Macrocells4 84 MacrocellsClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 Clock Generator 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O Cells8 I/O Cells 8I/O Cells 8Block C Block FBlock DBlock EBlock MXBlock LXRepeat Detail ABlock GBlock JBlock HBlock IBlock IXBlock HX Block JXBlock GX Repeat Detail ABlock KBlock N 8Block LBlock M 8 8Block EXBlock DX 8I/O CellsClock Generator8 4 84 I/O Cells8 I/O CellsClock GeneratorClock Generator4 84 48 48 I/O CellsClock Generator 48 48 1616Output SwitchMatrix16 1616Output SwitchMatrix16 Output SwitchMatrix16 16 16Output SwitchMatrix16 MacrocellsOE16 MacrocellsOEOE16 Macrocells16 MacrocellsOE16 16Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic Allocator 36 472 X 90AND Logic Arrayand Logic Allocator 36 44 72 X 90AND Logic Arrayand Logic Allocator36 4 72 X 90AND Logic Arrayand Logic Allocator36 24 2424 24 24 36 24 3636 24 36 24 Input SwitchMatrixInput SwitchMatrixInput SwitchMatrix72 X 90AND Logic Arrayand Logic AllocatorOE 16 472 X 90AND Logic Arrayand Logic AllocatorOE 16 44 OE72 X 90AND Logic Arrayand Logic Allocator16 4 OE72 X 90AND Logic Arrayand Logic Allocator16 16 16MacrocellsClock Generator 164 84 16 16Macrocells4 84 MacrocellsClock GeneratorClock Generator 48 416 16MacrocellsClock Generator 48 416 1616 16Output SwitchMatrix 8Output SwitchMatrix 8Output SwitchMatrix8 16 Output SwitchMatrix8 I/O Cells8 I/O Cells8 I/O Cells 8I/O Cells 8Block OBlock PBlock AXBlock BXInput SwitchMatrixInput SwitchMatrixInput SwitchMatrixBlock NXBlock KX Block FXBlock CX 16 Input SwitchMatrix17466G-068

ispMACH 4A Family35

ABSOLUTE MAXIMUM RATINGS

M4A5

Storage Temperature. . . . . . . . . . . . . . . -65°C to +150°CAmbient Temperature

with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°CDevice Junction Temperature. . . . . . . . . . . . . . . +130°CSupply Voltage

with Respect to Ground. . . . . . . . . . . . . -0.5 V to +7.0 VDC Input Voltage. . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 VStatic Discharge Voltage . . . . . . . . . . . . . . . . . . . .2000 VLatchup Current (TA = -40°C to +85°C) . . . . . . .200 mA

Stresses above those listed under Absolute MaximumRatings may cause permanent device failure. Functionalityat or above these limits is not implied. Exposure to AbsoluteMaximum Ratings for extended periods may affect devicereliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°CSupply Voltage (VCC)

with Respect to Ground . . . . . . . . . . +4.75 V to +5.25 V

Industrial (I) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . .-40°C to +85°CSupply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . +4.50 V to +5.5 V

Operating ranges define those limits between which the func-tionality of the device is guaranteed.

5-V DC CHARACTERISTICS OVER OPERATING RANGES

Parameter SymbolVOHVOLVIHVILIIHIILIOZHIOZLISC

Parameter DescriptionOutput HIGH VoltageOutput LOW VoltageInput HIGH VoltageInput LOW VoltageInput HIGH Leakage CurrentInput LOW Leakage CurrentOff-State Output Leakage Current HIGHOff-State Output Leakage Current LOWOutput Short-Circuit Current

Test Conditions

IOH = –3.2 mA, VCC = Min, VIN = VIH or VILIOH = –2.5 mA, VCC = Max, VIN = VIH or VILIOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1)Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2)

Guaranteed Input Logical LOW Voltage for all Inputs (Note 2)

VIN = 5.25 V, VCC = Max (Note 3)VIN = 0 V, VCC = Max (Note 3)

VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3)VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3)VOUT = 0.5 V, VCC = Max (Note 4)

–302.0

0.8 10–1010–10–160

Min2.4

3.60.5

Typ

Max

UnitVVVVVµAµAµAµAmA

Notes:

1.Total IOL for one PAL block should not exceed 64 mA.

2.These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.3.I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).

4.Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.

VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.

36ispMACH 4A Family

ABSOLUTE MAXIMUM RATINGS

M4A3

Storage Temperature. . . . . . . . . . . . . . . -65°C to +150°CAmbient Temperature

with Power Applied . . . . . . . . . . . . . . . .-55°C to +100°CDevice Junction Temperature. . . . . . . . . . . . . . . +130°CSupply Voltage

with Respect to Ground. . . . . . . . . . . . . -0.5 V to +4.5 VDC Input Voltage. . . . . . . . . . . . . . . . . . . . -0.5 V to 6.0 VStatic Discharge Voltage . . . . . . . . . . . . . . . . . . . .2000 VLatchup Current (TA = -40°C to +85°C) . . . . . . .200 mA

Stresses above those listed under Absolute MaximumRatings may cause permanent device failure. Functionalityat or above these limits is not implied. Exposure to AbsoluteMaximum Ratings for extended periods may affect devicereliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . . . 0°C to +70°CSupply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V

Industrial (I) Devices

Ambient Temperature (TA)

Operating in Free Air. . . . . . . . . . . . . . . .-40°C to +85°CSupply Voltage (VCC)

with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V

Operating ranges define those limits between which the func-tionality of the device is guaranteed.

3.3-V DC CHARACTERISTICS OVER OPERATING RANGES

Parameter SymbolVOHVOLVIHVILIIHIILIOZHIOZLISC

Parameter Description

Output HIGH Voltage

Test Conditions

VCC = Min

VIN = VIH or VILVCC = Min

VIN = VIH or VIL (Note 1)

IOH = –100 µAIOH = –3.2 mAIOL = 100 µAIOL = 24 mA

2.0–0.3MinVCC – 0.22.4

0.20.55.50.85–55–5

–15

–160

Typ

Max

UnitVVVVVVµAµAµAµAmA

Output LOW VoltageInput HIGH VoltageInput LOW VoltageInput HIGH Leakage CurrentInput LOW Leakage CurrentOff-State Output Leakage Current HIGHOff-State Output Leakage Current LOWOutput Short-Circuit Current

Guaranteed Input Logical HIGH Voltage for all Inputs

Guaranteed Input Logical LOW Voltage for all Inputs

VIN = 3.6 V, VCC = Max (Note 2)VIN = 0 V, VCC = Max (Note 2)VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2)VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2)VOUT = 0.5 V, VCC = Max (Note 3)

Notes:

1.Total IOL for one PAL block should not exceed 64 mA.

2.I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).

3.Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.Notes:

1.See “MACH Switching Test Circuit” document on the Literature Download page of the Lattice web site.

2.This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

ispMACH 4A Family37

ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1

-5

Combinatorial Delay:tPDitPD

Internal combinatorial propagation delay

Combinatorial propagation delaySynchronous clock setup time, D-type register

Synchronous clock setup time, T-type register

Asynchronous clock setup time, D-type register

Asynchronous clock setup time, T-type register

Synchronous clock hold timeAsynchronous clock hold timeSynchronous clock to internal outputSynchronous clock to outputAsynchronous clock to internal outputAsynchronous clock to outputSynchronous latch setup timeAsynchronous latch setup timeSynchronous latch hold timeAsynchronous latch hold timeTransparent latch to internal outputPropagation delay through transparent latch to output

Synchronous gate to outputAsynchronous gate to outputInput register setup time

1.52.5

3.01.52.5

3.51.5

1.52.5

3.51.5

4.03.00.03.0

5.57.03.04.56.07.5

1.52.5

3.0

1.52.5

3.81.5

3.55.0

4.05.5

4.36.0

4.56.5

5.07.5

7.010.0

9.012.0

11.014.0

nsns

-55

-6

-65

-7

-10

-12

-14

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxUnit

Registered Delays:tSStSSTtSAtSATtHStHAtCOSitCOStCOAitCOAtSSLtSALtHSLtHALtPDLitPDL

3.04.02.53.00.02.5

2.54.05.06.5

4.03.00.03.0

5.57.03.04.56.07.5

2.03.0

3.0

2.03.0

4.01.5

3.54.02.53.00.02.5

2.54.05.06.5

4.03.50.03.5

5.87.53.04.86.07.8

2.03.0

3.0

2.03.0

4.02.0

3.54.02.53.00.02.5

2.84.55.06.8

4.53.50.03.5

6.08.03.05.06.08.0

2.03.0

3.5

2.03.0

4.02.0

3.54.03.03.50.03.0

3.05.05.07.0

6.04.00.04.0

7.510.03.56.08.511.0

2.03.0

4.5

2.03.0

4.02.0

5.06.03.54.50.03.5

3.05.56.08.5

7.04.00.04.0

9.012.04.57.510.013.0

2.03.0

6.0

2.04.0

5.02.0

5.56.54.05.00.04.0

3.06.08.011.0

8.05.00.05.0

11.014.07.010.013.016.0

2.04.0

6.0

7.08.05.06.00.05.0

3.56.510.013.0

10.08.00.08.0

12.015.08.011.015.018.010.011.08.09.00.08.0

3.56.512.015.0

nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns

Latched Delays:

tGOSiSynchronous gate to internal outputtGOStGOAtSIRS

tGOAiAsynchronous gate to internal outputInput Register Delays:tHIRSInput register hold time

tICOSiInput register clock to internal feedbackInput Latch Delays:tSILtHIL

Input latch setup time Input latch hold time

Transparent input latch to internal feedback

tIGOSiInput latch gate to internal feedbacktPDILi

38ispMACH 4A Family

ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5

Input Register Delays with ZHT Option:tSIRZ

Input register setup time - ZHT

6.00.06.00.0

6.0

6.00.06.00.0

6.0

6.00.06.00.0

6.0

6.00.06.00.0

6.0

6.00.06.00.0

6.0

6.00.06.00.0

6.0

6.00.06.00.0

6.0

6.00.06.00.0

6.0

nsnsnsnsns

tHIRZInput register hold time - ZHTInput Latch Delays with ZHT Option:tSILZ

Input latch setup time - ZHTtHILZInput latch hold time - ZHTtPDILTransparent input latch to internal

feedback - ZHTZi

Output Delays:tBUFtSLWtEAtERtPL

Output buffer delaySlow slew rate delay adderOutput enable timeOutput disable timePower-down mode delay adderAsynchronous reset or preset to internal register output

Asynchronous reset or preset to register output

Asynchronous reset and preset register recovery time

Asynchronous reset or preset widthGlobal clock width lowGlobal clock width highProduct term clock width lowGlobal gate width low (for low transparent) or high (for high transparent)

Product term gate width low (for low transparent) or high (for high transparent)

7.07.02.02.03.03.04.0

1.52.57.57.52.5

1.52.57.57.52.5

1.82.58.58.52.5

2.02.58.58.52.5

2.52.59.59.52.5

3.02.510.010.02.5

3.02.512.012.02.5

3.02.515.015.02.5

nsnsnsnsns

-55

-6

-65

-7

-10

-12

-14

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxUnit

Power Delay:

Reset and Preset Delays:tSRitSRtSRRtSRWtWLStWHStWLA

7.59.0

7.07.02.02.03.03.04.0

7.79.2

7.58.02.52.53.53.54.5

8.010.0

7.58.02.52.53.53.54.5

8.010.0

8.010.03.03.04.04.05.0

9.512.0

8.010.04.04.05.05.05.0

11.014.0

10.012.05.05.08.08.06.0

13.016.0

15.015.06.06.09.09.06.0

16.019.0

nsnsnsnsnsnsnsnsns

Clock/LE Width:

tWHAProduct term clock width hightGWS

tGWA

4.03.03.04.0

4.03.03.04.0

4.53.53.54.5

4.53.53.54.5

5.04.04.05.0

5.05.05.05.0

6.06.06.06.0

9.06.06.06.0

nsnsnsns

tWIRLInput register clock width lowtWIRHInput register clock width hightWIL

Input latch gate width

ispMACH 4A Family39

ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)

-5

Frequency:

External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS)

143

133125167154250111105133125167167

125118160148200108102125125143143

11811115414320010095.2125118143143

95.287.012511115483.376.910595.2125125

87.080.011810512566.762.583.376.9100100

74.169.095.087.010055.652.666.762.562.583.3

60.657.174.169.083.343.541.750.047.655.683.3

MHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHz

-55

-6

-65

-7

-10

-12

-14

MinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxUnit

External feedback, T-type, Min of 1/(tWLS

125

+ tWHS) or 1/(tSST + tCOS)fMAXS

Internal feedback (fCNT), D-type, Min of

182

1/(tWLS + tWHS) or 1/(tSS + tCOSi)

Internal feedback (fCNT), T-type, Min of

154

1/(tWLS + tWHS) or 1/(tSST + tCOSi)No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 1/(tSST + tHS)External feedback, D-type, Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA)

250111

External feedback, T-type, Min of 1/(tWLA

105

+ tWHA) or 1/(tSAT + tCOA)fMAXA

Internal feedback (fCNTA), D-type, Min of

133

1/(tWLA + tWHA) or 1/(tSA + tCOAi)

Internal feedback (fCNTA), T-type, Min of

125

1/(tWLA + tWHA) or 1/(tSAT + tCOAi)No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA)fMAXI

167

Maximum input register frequency, Min

167

of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS)

Notes:

1.See “Switching Test Circuit” document on the Literature Download page of the Lattice web site.

2.This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

CAPACITANCE 1

Parameter SymbolCINCI/O

Parameter DescriptionInput capacitanceOutput capacitance

VIN=2.0 VVOUT=2.0V

Test Conditions

3.3 V or 5 V, 25°C, 1 MHz3.3 V or 5 V, 25°C, 1 MHz

Typ68

UnitpFpF

Note:

1.These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified

where this parameter may be affected.

40ispMACH 4A Family

ICC vs. FREQUENCY

These curves represent the typical power consumption for a particular device at system frequen-cy. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and ex-ercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The low-est frequency signals (MSBs) are placed in a common PAL block and set to lowest power.

400350300250

ICC (mA)200

M4A-192/96150100500

100140120160180200M4A-512/160M4A-384/160M4A-256/160M4A-256/128M4A-192/96

100

M4A-96/48M4A-128/64M4A-64/64M4A-64/32

M4A-32/32

0

100120140160180200204060800204060800M4A-96/48M4A-128/64M4A-64/64M4A-64/32M4A-32/32VCC = 5 V or 3.3 V, TA = 25º CM4A-512/160M4A-384/160M4A-256/160M4A-256/128Frequency (MHz)

Figure 19. ispMACH 4A ICC Curves at High Speed Mode

250

VCC = 5 V or 3.3 V, TA = 25º C

200

ICC (mA)150

50

Frequency (MHz)

Figure 20. ispMACH 4A ICC Curves at Low Power Mode

ispMACH 4A Family41

44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)

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44-Pin PLCC

A3A4A5A6A7B7B6I/O30D6B5I/O29D5B4I/O28D4M4A(3,5)-64/32M4A(3,5)-64/326A2A1A0A2A1A0I/O5I/O6I/O7TDIM4A(3,5)-32/32CLK0/I0GNDTCKA8A9A10A11B0B1I/O8I/O97891011121314151617543214443424140393837I/O27I/O26I/O25I/O24TDOGNDCLK1/I1TMSI/O23I/O22I/O21C0C1C2B8B9B10M4A(3,5)-32/32D3D2D1D0B3B2B1B0C7I/O31D7I/O4A3I/O3A4I/O2A5I/O1A6I/O0A7GNDVCC3635343332313029I/O CellPAL BlockB2I/O10B3I/O111819202122232425262728VCCB4I/O12B5I/O13B6I/O14B7I/O15GNDC7I/O16C6I/O17C5I/O18C4I/O19M4A(3,5)-64/32C3I/O20B11M4A(3,5)-64/32A12A13A14A15B15B14B13B1217466G-026

PIN DESIGNATIONS

CLK/I=Clock or InputGND=GroundI/OVCCTDITCKTMS

=Input/Output=Supply Voltage=Test Data In=Test Clock=Test Mode Select

TDO=Test Data Out

42ispMACH 4A Family

44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)

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44-Pin TQFP

A3A4A5A6A7B7B6B5B4D7D6D5D4A2A1A0M4A(3,5)-32/32A8A9A10A11I/O5I/O6I/O7TDICLK0/I0GNDTCKI/O8B0I/O9B1B2I/O10B3I/O11A2A1A012345678910114443424140393837363534I/O4I/O3I/O2I/O1I/O0GNDVCCI/O31I/O30I/O29I/O28M4A(3,5)-64/32A3A4A5A6A7M4A(3,5)-64/32C7I/O CellPAL Block3332313029282726252423I/O27D3I/O26D2I/O25D1I/O24D0TDOGNDCLK1/I1TMSI/O23C0I/O22C1I/O21C2B3B2B1B0M4A(3,5)-32/32B8B9B10M4A(3,5)-64/32I/O12I/O13I/O14I/O15VCCGNDI/O16I/O17I/O18I/O19I/O201213141516171819202122M4A(3,5)-64/32B4B5B6B7A12A13A14A15PIN DESIGNATIONS

CLK/I=Clock or InputGND=GroundI/OVCCTDITCKTMS

=Input/Output=Supply Voltage=Test Data In=Test Clock=Test Mode Select

TDO=Test Data Out

ispMACH 4A Family

B15B14B13B12B11C7C6C5C4C343

48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32)

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48-Pin TQFP

A3A4A5A6A7A2A1A0M4A(3,5)-32/32A8A9A10A11I/O5I/O6I/O7TDICLK0/I0NCGNDTCKB0I/O8B1I/O9B2I/O10B3I/O11A2A1A0123456789101112484746454443424140393837I/O4I/O3I/O2I/O1I/O0GNDNCVCCI/O31I/O30I/O29I/O28M4A(3,5)-64/32D7D6D5D4A3A4A5A6A7B7B6B5B4M4A(3,5)-64/32C7I/O CellPAL Block363534333231302928272625I/O27D3I/O26D2I/O25D1I/O24D0TDOGNDNCCLK1/I1TMSI/O23C0I/O22C1I/O21C2B3B2B1B0M4A(3,5)-32/32B8B9B10M4A(3,5)-64/32I/O12I/O13I/O14I/O15VCCNCGNDI/O16I/O17I/O18I/O19I/O20131415161718192021222324M4A(3,5)-64/32A12A13A14A15B15B14B13B12B11C7C6C5C4C3B4B5B6B717466G-028

PIN DESIGNATIONS

CLK/I=Clock or InputGND=GroundI/OVCCNCTDITCKTMS

=Input/Output=Supply Voltage=No Connect=Test Data In=Test Clock=Test Mode Select

TDO=Test Data Out

44ispMACH 4A Family

100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48)

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100-Pin TQFPA2A3A4A5A6A7GNDNCNCI/O5I/O4I/O3I/O2I/O1I/O0I7VCCGNDNCNCI6NCI/O47I/O46I/O45I/O44I/O43I/O42NCNCGNDNCTDINCNCA1I/O6A0I/O7B0I/O8B1I/O9B2I/O10B3I/O11I0/CLK0VCCGNDI1/CLK1B4I/O12B5I/O13B6I/O14B7I/O15C0I/O16C1I/O17NCNCTMSTCKNC100999897969594939291908988878685848382818079787776F7F6F5F4F3F212345678910111213141516171819202122232425C7I/O CellPAL Block75747372717069686766656463626160595857565554535251NCTDONCNCNCI/O41I/O40I/O39I/O38I/O37I/O36I5/CLK3GNDVCCI4/CLK2I/O35I/O34I/O33I/O32I/O31I/O30NCNCNCNCF1F0E0E1E2E3E4E5E6E7D0D1C2C3C4C5C6C7D7D6D5D4D3D2GNDNCNCI/O18I/O19I/O20I/O21I/O22I/O23NCI2NCNCGNDVCCI3I/O24I/O25I/O26I/O27I/O28I/O29NCNCGND2627282930313233343536373839404142434445464748495017466G-029

PIN DESIGNATIONS

CLK/I=Clock or InputGND=GroundII/OVCCNCTDITCKTMS

=Input=Input/Output=Supply Voltage=No Connect=Test Data In=Test Clock=Test Mode Select

TDO=Test Data Out

ispMACH 4A Family

45

100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64)

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100-Pin PQFP

A7A6A5A4A3A2A1A0I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCCGNDGNDVCCI/O63I/O62I/O61I/O60I/O59I/O58I/O57I/O56(10)100(9)99(8)98(7)97(6)96(5)95(4)94(3)93I/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31VCCGNDGNDVCCI/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O3931(33)32(34)33(35)34(36)35(37)36(38)37(39)38(40)3940414243(45)44(46)45(47)46(48)47(49)48(50)49(51)50(52)GNDGNDTDII5B7I/O8B6I/O9B5I/O10B4I/O11B3I/O12B2I/O13B1I/O14B0I/O15IO/CLK0VCCVCCGNDGNDI1/CLK1C0I/O16C1I/O17C2I/O18C3I/O19C4I/O20C5I/O21C6I/O22C7I/O23TMSTCKGNDGND1234 (83)5(12)6(13)7(14)8(15)9(16)10(17)11(18)12(19)13(20)1415161718(23)19(24)20(25)21(26)22(27)23(28)24(29)25(30)26(31)27282930(82)(81)(80)(79)(78)(77)(76)(75)929190898887868584838281H0H1H2H3H4H5H6H7C7I/O Cell PAL Block80797877(73)76(72)75(71)74(70)73(69)72(68)71(67)70(66)69(65)6867666564(62)63(61)62(60)61(59)60(58)59(57)58(56)57(55)56(54)55(41)54535251GNDGNDTD0TRSTG7I/O55G6I/O54G5I/O53I/O52G4I/O51G3I/O50G2I/O49G1I/O48G0I4/CLK3GNDGNDVCCVCCI3/CLK2I/O47F0F1I/O46F2I/O45F3I/O44F4I/O43F5I/O42F6I/O41F7I/O40I2ENABLEGNDGNDPIN DESIGNATIONS

I/CLK=Input or ClockGND=GroundII/OVCCTDITCKTMS

=Input=Input/Output=Supply Voltage=Test Data In=Test Clock=Test Mode Select

TDO=Test Data OutTRST=Test ResetENABLE = Program

46

D7D6D5D4D3D2D1D0ispMACH 4A Family

E0E1E2E3E4E5E6E717466G-031

100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64)

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100-Pin TQFP

M4A3-128/64M4A5-128/64M4A3-64/64H0H1H2H3H4H5H6H7D0D2D4D6D8D10D12D14A7A6A5A4A3A2A1A0GNDTDII/O8A1I/O9A3A5I/O10A7I/O11A9I/O12A11I/O13A13I/O14A15I/O15I0/CLK0VCCGNDI1/CLK1I/O16B15I/O17B13I/O18B11I/O19B9I/O20B7I/O21B5I/O22B3I/O23B1TMSTCKGNDA14A12A10A8A6A4A2A0100999897969594939291908988878685848382818079787776GNDGNDI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0VCCGNDGNDVCCI5I/O63I/O62I/O61I/O60I/O59I/O58I/O57I/O56GNDGNDB7B6B5B4B3B2B1B0C0C1C2C3C4C5C6C712345678910111213141516171819202122232425C7I/O CellPAL Block75747372717069686766656463626160595857565554535251GNDTDOTRSTI/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O48I4/CLK3GNDVCCI3/CLK2I/O47I/O46I/O45I/O44I/O43I/O42I/O41I/O40ENABLEGNDD1D3D5D7D9D11D13D15G7G6G5G4G3G2G1G0C15C13C11C9C7C5C3C1F0F1F2F3F4F5F6F7B14B12B10B8B6B4B2B0C0C2C4C6C8C10C12C14GNDGNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31I2VCCGNDGNDVCCI/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39GNDGND2627282930313233343536373839404142434445464748495017466G-032a

D7D6D5D4D3D2D1D0PIN DESIGNATIONS

CLK/I=Clock or InputGND=GroundII/OVCCTDITCKTMS

=Input=Input/Output=Supply Voltage=Test Data In=Test Clock=Test Mode Select

TDO=Test Data OutTRST=Test ResetENABLE = Program

ispMACH 4A Family

E0E1E2E3E4E5E6E747

100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64)

Bottom View

100-Ball caBGA

10AGND9I/O63H7GND8I/O60H4I/O61H5I/O62H6GNDI/O51G3I/O40F0I/O42F2I/O46F6GNDI/O36E487I/O57H1I5I/O58H2I/O59H3I/O54G6I/O52G4I/O43F3GNDI/O38E6I/O33E176GND5GNDI/O0A0I/O2A2I/O5A5I/O16C0VCCI/O35E3I/O24D0VCC4I/O1A1I/O6A6GNDI/O11B3I/O20C4I/O22C6I/O27D3I/O26D2I2I/O25D143I/O4A4GNDI/O14B6I/O10B2I/O8B0I/O19C3GNDI/O30D6I/O29D5I/O28D432I/O7A7TDII/O13B5CLK0/I01GNDI/O15B7I/O12B4I/O9B1GNDABTRSTI/O53G5I/O50G2CLK3/I3VCCI/O56H0I/O3A3VCCI/O48G0I/O37E5I/O34E2I/O32E0GND6BCTDOI/O55G7I/O49G1VCCCDDEVCCI/O17C1I/O23C7TCKEFGNDI/O41F1I/O44F4I/O47F7GND10CLK1/I1FI/O18C2I/O21C5TMSGCLK2/I2I/O45F5ENABLEI/O39E79GHHJGNDI/O31D72JKGND5GND1KPIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O CellPAL Block17466G-100cabga

48ispMACH 4A Family

144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96)

Top View

144-Pin TQFP

B7B6B5B4B3B2B1B0A7A6A5A4A3A2A1A0L0L1L2L3L4L5L6L7D7D6D5D4D3D2D1D0C7C6C5C4C3C2C1C0E7E6E5E4E3E2E1E0GNDTDII/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7I2I3VCCGNDI4I/O8I/O9I/O10I/O11I/O12I/O13I/O14I/O15GNDVCCI/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23TMSTCKGND144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109I/O95I/O94I/O93I/O92I/O91I/O90I/O89I/O88GNDVCCI/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O80I1I0CLK0GNDVCCCLK3I15I14I13I/O79I/O78I/O77I/O76I/O75I/O74I/O73I/O72GND123456789101112131415161718192021222324252627282930313233343536C7I/O CellPAL Block108107106105104103102101100999897969594939291908988878685848382818079787776757473GNDTDONCI/O71I/O70I/O69I/O68I/O67I/O66I/O65I/O64I12VCCGNDI11I10I/O63I/O62I/O61I/O60I/O59I/O58I/O57I/O56GNDVCCI/O55I/O54I/O53I/O52I/O51I/O50I/O49I/O48NCGNDK0K1K2K3K4K5K6K7J0J1J2J3J4J5J6J7I0I1I2I3I4I5I6I7F7F6F5F4F3F2F1F0G0G1G2G3G4G5G6G7H0H1H2H3H4H5H6H7GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31I5I6I7CLK1GNDVCCCLK2I8I9I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39VCCGNDI/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O4737383940414243444546474849505152535455565758596061626364656667686970717217466G-033

PIN DESIGNATIONS

CLK

=ClockGND=GroundII/OVCCTDITCKTMS

=Input=Input/Output=Supply Voltage=Test Data In=Test Clock=Test Mode Select

TDO=Test Data Out

ispMACH 4A Family49

144-BALL fpBGA CONNECTION DIAGRAM (M4A3-192/96)

Bottom View

144-Ball fpBGA

12ABCDEFGHJKLMGND11I/O95L7I/O94L6TDOI/O82K2I/O87 K7I11I/O74J2I/O78J6I/O65 I1I/O67 I3I/O71I7I/O63H710I/O91L3I/O90L2I/O93 L5I/O80K0I/O85 K5GNDI/O73 J1I/O77J5VCCI/O70I6I/O62H6I/O61H59I13I/O88L0I14I/O92L4I/O81 K1I/086 K6I/O72J0I/O76J4I/O69 I5I/O60H4I/O58H2I/O56H08GBCLK37I06I/O2 A2I/O3 A3I/O4A4VCCI/O9 B1I35I/O6 A6I/O7A7GNDI/O11 B3I/O26D2GNDI/O35E3I/O41F1GBCLK24I/O8 B0I/O10B2I/O12 B4I/O29 D5I/O23 C7I/O19 C3I/O38E6I/O33E1I/O44F4I6I/O40F0I53I/O13B5I/O14 B6I/O30 D6I22I/O15 B7I/O31D7I/O27 D3I/O25 D1GNDI/O21C5I/O17C1I/O39E7I/O34E2TCKI/O46F6I/O47F71GNDABCDEFGHJKLMGNDVCCI1I/O0A0I/O1A1I/O5A5I15TDII/O28D4I/O24 D0VCCI/O22 C6I/O18C2VCCI/O36E4TMSGNDI/O84 K4I12GNDGBCLK0I/O89 L1I/O83K3VCCI/O66I2I/O59H3GNDI/O55G7I/O54G6I4I/O20 C4I/O16C0I/O37 E5I/O32E0I/O45F5I/O42F2I/O43F3I10I/O75 J3I/O79J7I/O64I0I/O68 I4GNDGNDI/O57 H1VCCI/O52G4I/O51G3I/O50G2I7I/O53 G5I/O49 G1I/O48G0I9VCCGNDGNDGNDI8GBCLK1GND121110987654321PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O CellPAL Blockm4a3.192.96_144bga

50ispMACH 4A Family

208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 ANDM4A3-256/160)

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208-Pin PQFP

O8O9O10O11O12O13O14O15B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0A14A12P12P14O0O1O2O3O4O5O6O7A6A4P4P6O0O1O2O3O4O5O6O7B7B6B5B4B3B2B1B0A7A6A5A4A3A2A1A0P0P1P2P3P4P5P6P7GNDI/O19I/O18I/O17I/O16I/O15I/O14I/O13I/O12GNDVCCI/O11I/O10I/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2CLK0VCCGNDI/O1I/O0I/O159I/O158GNDVCCCLK3I/O157I/O156I/O155I/O154I/O153I/O152I/O151I/O150I/O149I/O148VCCGNDI/O147I/O146I/O145I/O144I/O143I/O142I/O141I/O140GNDM4A3-256/160208207206205204203202201200199198197196195194193192191190189188187186185184183182181180179178177176175174173172171170169168167166165164163162161160159158157GNDI/O15I/O14I/O13I/O12I/O11I/O10I/O9I/O8GNDVCCI/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0I1I0CLK0VCCGNDGNDVCCVCCGNDGNDVCCCLK3I13I12I/O127I/O126I/O125I/O124I/O123I/O122I/O121I/O120VCCGNDI/O119I/O118I/O117I/O116I/O115I/O114I/O113I/O112GNDM4A(3, 5)-256/128C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1C0D14D12D6D4E0E2E6E10F0F1F2F3F4F5F6F7F8F9F10F11F12F13F14F15GNDTDII/O20I/O21I/O22I/O23I/O24I/O25I/O26I/O27VCCGNDI/O28I/O29I/O30I/O31I/O32I/O33I/O34I/O35I/O36I/O37GNDVCCI/O38I/O39I/O40I/O41I/O42GNDI/O43I/O44I/O45I/O46I/O47I/O48I/O49I/O50I/O51GNDVCCI/O52I/O53I/O54I/O55I/O56I/O57I/O58I/O59TMSTCKGNDC7C6C5C4C3C2C1C0D7D6D5D4D3D2D1D0E0E1E2E3E4E5E6E7F0F1F2F3F4F5F6F7GNDTDII/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23VCCGNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31I2I3GNDVCCVCCGNDGNDVCCVCCGNDI4I/O32I/O33I/O34I/O35I/O36I/O37I/O38I/O39GNDVCCI/O40I/O41I/O42I/O43I/O44I/O45I/O46I/O47TMSTCKGND12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInput Input/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7156155RECOMMEND TO TIE TO VCC154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125I/O Cell124123PAL Block122121120119118117116115114113112111110109108107RECOMMEND TO TIE TO GND106105GNDTDOTRSTI/O111I/O110I/O109I/O108I/O107I/O106I/O105I/O104VCCGNDI/O103I/O102I/O101I/O100I/O99I/O98I/O97I/O96I11GNDVCCVCCGNDGNDVCCVCCGNDI10I9I/O95I/O94I/O93I/O92I/O91I/O90I/O89I/O88GNDVCCI/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O80ENABLEGNDN7N6N5N4N3N2N1N0M7M6M5M4M3M2M1M0L0L1L2L3L4L5L6L7K0K1K2K3K4K5K6K7GNDTDONCI/O139I/O138I/O137I/O136I/O135I/O134I/O133I/O132VCCGNDI/O131I/O130I/O129I/O128I/O127I/O126I/O125I/O124I/O123GNDI/O122I/O121I/O120I/O119I/O118VCCGNDI/O117I/O116I/O115I/O114I/O113I/O112I/O111I/O110I/O109I/O108GNDVCCI/O107I/O106I/O105I/O104I/O103I/O102I/O101I/O100NCGNDN15N14N13N12N11N10N9N8N7N6N5N4N3N2N1N0M10M6M2M0L4L6L12L14K0K1K2K3K4K5K6K7K8K9K10K11K12K13K14K15G7G6G5G4G3G2G1G0H7H6H5H4H3H2H1H0G15G14G13G12G11G10G9G8I12I14J0J1J2J3J4J5J6J7G7G6G5G4G3G2G1G0H14H12J8J9J10J11J12J13J14J15H6H4I4I6GNDI/O60I/O61I/O62I/O63I/O64I/O65I/O66I/O67GNDVCCI/O68I/O69I/O70I/O71I/O72I/O73I/O74I/O75I/O76I/O77CLK1VCCGNDI/O78I/O79I/O80I/O81GNDVCCCLK2I/O82I/O83I/O84I/O85I/O86I/O87I/O88I/O89I/O90I/O91VCCGNDI/O92I/O93I/O94I/O95I/O96I/O97I/O98I/O99GNDJ0J1J2J3J4J5J6J7I0I1I2I3I4I5I6I7GNDI/O48I/O49I/O50I/O51I/O52I/O53I/O54I/O55GNDVCCI/O56I/O57I/O58I/O59I/O60I/O61I/O62I/O63I5I6CLK1VCCGNDGNDVCCVCCGNDGNDVCCCLK2I7I8I/O64I/O66I/O66I/O67I/O68I/O69I/O70I/O71VCCGNDI/O72I/O73I/O74I/O75I/O76I/O77I/O78I/O79GND535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310417466G-044

ispMACH 4A Family51

208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160)

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208-Pin PQFP

XO0XO1XO2XO3XO4XO5XO6XO7XH6XH7XE0XE1XE2XE3XE4XE5XE6XE7XG0XG1XG2XG3XG4XG5XG6XG7B7B6B5B4B3B2B1B0D7D6D5D4D3D2D1D0A7A6A4A1XH1XH4GNDI/O17I/O16I/O15I/O14I/O13I/O12I/O11I/O10GNDVCCI/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0CLK0VCCGNDI/O159I/O158I/O157I/O156GNDVCCCLK3I/O155I/O154I/O153I/O152I/O151I/O150I/O149I/O148I/O147I/O146VCCGNDI/O145I/O144I/O143I/O142I/O141I/O140I/O139I/O138GNDXP6XP7XN0XN1XN2XN3XN4XN5XN6XN7A4A1XP1XP4C7C6C5C4C3C2C1C0A7A6B7B6B5B4B3B2B1B0M4A3-512/160M4A3-384/160F7F6F5F4F3F2F1F0G7G6G5G4G3G2G1G0E7E5E2E0L0L2L3L5J0J1J2J3J4J5J6J7K0K1K2K3K4K5K6K7GNDTDII/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25VCCGNDI/O26I/O27I/O28I/O29I/O30I/O31I/O32I/O33I/O34I/O35GNDVCCI/O36I/O37I/O38I/O39I/O40GNDI/O41I/O42I/O43I/O44I/O45I/O46I/O47I/O48I/O49GNDVCCI/O50I/O51I/O52I/O53I/O54I/O55I/O56I/O57TMSTCKGND208207206205204203202201200199198197196195194193192191190189188187186185184183182181180179178177176175174173172171170169168167166165164163162161160159158157GNDI/O17I/O16I/O15I/O14I/O13I/O12I/O11I/O10GNDVCCI/O9I/O8I/O7I/O6I/O5I/O4I/O3I/O2I/O1I/O0CLK0VCCGNDI/O159I/O158I/O157I/O156GNDVCCCLK3I/O155I/O154I/O153I/O152I/O151I/O150I/O149I/O148I/O147I/O146VCCGNDI/O145I/O144I/O143I/O142I/O141I/O140I/O139I/O138GNDC7C6C5C4C3C2C1C0F7F6F5F4F3F2F1F0E7E5E2E0H0H2H3H5G0G1G2G3G4G5G6G7J0J1J2J3J4J5J6J7GNDTDII/O18I/O19I/O20I/O21I/O22I/O23I/O24I/O25VCCGNDI/O26I/O27I/O28I/O29I/O30I/O31I/O32I/O33I/O34I/O35GNDVCCI/O36I/O37I/O38I/O39I/O40GNDI/O41I/O42I/O43I/O44I/O45I/O46I/O47I/O48I/O49GNDVCCI/O50I/O51I/O52I/O53I/O54I/O55I/O56I/O57TMSTCKGND12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInput Input/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7156155RECOMMEND TO TIE TO VCC154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125I/O Cell124123PAL Block122121120119118117116115114113112111110109108107RECOMMEND TO TIE TO GND106105GNDTDONCI/O137I/O136I/O135I/O134I/O133I/O132I/O131I/O130VCCGNDI/O129I/O128I/O127I/O126I/O125I/O124I/O123I/O122I/O121GNDI/O120I/O119I/O118I/O117I/O116VCCGNDI/O115I/O114I/O113I/O112I/O111I/O110I/O109I/O108I/O107I/O106GNDVCCI/O105I/O104I/O103I/O102I/O101I/O100I/O99I/O98NCGNDXF7XF6XF5XF4XF3XF2XF1XF0XC7XC6XC5XC4XC3XC2XC1XC0XD5XD3XD2XD0XA0XA2XA5XA7XB0XB1XB2XB3XB4XB5XB6XB7O0O1O2O3O4O5O6O7GNDTDONCI/O137I/O136I/O135I/O134I/O133I/O132I/O131I/O130VCCGNDI/O129I/O128I/O127I/O126I/O125I/O124I/O123I/O122I/O121GNDI/O120I/O119I/O118I/O117I/O116VCCGNDI/O115I/O114I/O113I/O112I/O111I/O110I/O109I/O108I/O107I/O106GNDVCCI/O105I/O104I/O103I/O102I/O101I/O100I/O99I/O98NCGNDXK7XK6XK5XK4XK3XK2XK1XK0XJ7XJ6XJ5XJ4XJ3XJ2XJ1XJ0XL5XL3XL2XL0XE0XE2XE5XE7XG0XG1XG2XG3XG4XG5XG6XG7XF0XF1XF2XF3XF4XF5XF6XF7L4L1M1M4M6M7P0P1P2P3P4P5P6P7XA6XA7XC0XC1XC2XC3XC4XC5XC6XC7O7O6O5O4O3O2O1O0N7N6N5N4N3N2N1N0P7P6P4P1XA1XA4XB0XB1XB2XB3XB4XB5XB6XB7GNDI/O58I/O59I/O60I/O61I/O62I/O63I/O64I/O65GNDVCCI/O66I/O67I/O68I/O69I/O70I/O71I/O72I/O73I/O74I/O75CLK1VCCGNDI/O76I/O77I/O78I/O79GNDVCCCLK2I/O80I/O81I/O82I/O83I/O84I/O85I/O86I/O87I/O88I/O89VCCGNDI/O90I/O91I/O92I/O93I/O94I/O95I/O96I/O97GNDN0N1N2N3N4N5N6N7K7K6K5K4K3K2K1K0I7I6I5I4I3I2I1I0L7L6GNDI/O58I/O59I/O60I/O61I/O62I/O63I/O64I/O65GNDVCCI/O66I/O67I/O68I/O69I/O70I/O71I/O72I/O73I/O74I/O75CLK1VCCGNDI/O76I/O77I/O78I/O79GNDVCCCLK2I/O80I/O81I/O82I/O83I/O84I/O85I/O86I/O87I/O88I/O89VCCGNDI/O90I/O91I/O92I/O93I/O94I/O95I/O96I/O97GND535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310417466Ga-044

52ispMACH 4A Family

256-BALL BGA CONNECTION DIAGRAM (M4A(3,5)-256/128)

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256-Ball BGA

20ABCDEFGNDGNDI/O116O3I/O120P7I/O123P4GND19N/CI/O113O6N/CI/O117O2I/O119O0I/O122P5I/O125P2I/O127P0N/CCLK318GNDN/CVCCI/O112O7I/O114O5I/O118O1I/O121P6I/O126P1N/CN/C17I/O108N4I/O109N5TRSTVCCTDII/O115O4VCCI/O124P3I13N/C16I/O105N1I/O106N2I/O111N7VCC15GNDI/O103M7I/O107N3I/O110N614I/O100M4I/O102M6I/O104N0VCC13I/O96M0I/O98M2I/O101M5N/C12GNDN/CI/O97M1I/O99M311GNDI11N/CN/C10GNDN/CI10I99GNDN/CI/O94L1I/O92L38I/O95L0I/O93L2I/O90L5N/C7I/O91L4I/O89L6I/O86K1VCC6GNDI/O88L7I/O84K3I/O81K65I/O87K0I/O85K2I/O80K7VCC4N/CI/O83K4ENABLEVCCTDOI/O76J4VCCI/O67I3I7N/C3GNDI/O82K5VCCI/O79J7I/O77J5I/O73J1I/O70I6I/O66I2N/CN/C2GNDN/CI/O78J6I/O75J3I/O72J0I/O69I5I/O65I1I/O64I0N/CCLK21GNDGNDI/O74J2I/O71I7I/O68I4GNDABCDEFGHJKI12GNDN/CGNDPIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramI8GNDN/CN/CGHJKLMNPRTN/CN/CGNDI1GNDI/O4A4I/O7A7I/O10B2GNDGND20CLK0N/CI/O0A0I/O1A1I/O5A5I/O8B0I/O11B3I/O13B5I/O14B6GND19N/CN/CI/O2A2I/O6A6I/O9B1I/O12B4I/O15B7VCCN/CGND18N/CI0I/O3A3VCCN/CTCKN/CN/CN/CI/O61H2I/O57H6I/O54G1I/O50G5I/O48G7VCCN/CGND3CLK1I/O63H0I/O59H4I/O58H5I/O56H7I/O55G0I/O53G2I/O52G3I/O49G6N/C2GNDI/O62H1GNDI5GNDN/CLMNPRTC7I/O CellPAL BlockI6I/O60H3VCCI/O51G4TMSUVWYVCCI/O16C7N/CN/C17VCCI/O17C6I/O19C4I/O20C316I/O18C5I/O21C2I/O22C1GND15VCCI/O23C0I/O25D6I/O26D514I/O24D7I/O27D4I/O28D3I/O30D113I/O29D2I/O31D0N/CGND12I2I3N/CGND11N/CN/CI4GND10I/O35E3I/O33E1N/CGND9N/CI/O37E5I/O34E2I/O32E08VCCI/O41F1I/O38E6I/O36E47N/CI/O43F3I/O39E7GND6VCCI/O46F6I/O42F2I/O40F05VCCI/O47F7I/O45F5I/O44F44N/CN/CGNDGND1UVWY17466G-045

ispMACH 4A Family53

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192)

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256-Ball fpBGA

16ABCDEFGHJKLMNPRTI/O167N15I/O165N13I/O163N11I/O158N6I/O156N4I/O152N0I/O147M6I/O144M0I/O138L4I/O143L14I/O124K4I/O128K8I/O132K12I/O134K14I/O116J12I/O114J1015I/O181O13I/O166N14I/O164N12I/O159N7NCI/O157N5I/O150M12I/O146M4I/O139L6I/O120K0I/O125K5I/O129K9I/O133K13I/O117J13I/O115J11I/O113J914I/O180O12I/O182O14NCTDOI/O162N10I/O155N3I/O149M10I/145OM2I/O140L8I/O121K1I/O127K7I/O131K11I/O135K15I/O118J14I/O112J8I/O110J613I/O177O9I/O179O11I/O183O15GNDVCCGNDVCCGNDGNDVCCGNDGNDVCCI/O119J15I/O111J7I/O109J512I/O174O6I/O175O7I/O178O10GNDI/O160N8I/O154N2I/O148M8I/O136L0I/O142L12I/O123K3I/O130K10I/O107J3GNDI/O108J4I/O104J011I/O172O4I/O173O5I/O170O2VCCI/O161N9I/O153N1I/O151M14I/O137L2I/O141L10I/O122K2I/O126K6I/O105J1VCCI/O106J2I/O102I1210I/O191P14I/O168O0I/O171O3GND9I/O186P4I/O187P6I/O189P10VCC8I/O1A2I/O0A0I/O184P0GND7I/O3A6I/O5A10I/O6A12GNDI/O2A4I/O4A8VCCGNDGNDVCCI/O77G5I/O80G8GNDI/O94H12I/O72G0I/O95H146GCLK0I/O7A14I/O12B4VCCI/O8B0I/O11B3I/O33C9I/O27C3I/O46D12I/O41D2I/O52E8I/O83G11VCCI/O79G7I/O76G4I/O73G15I/O9B1I/O10B2I/O14B6GNDNCI/O34C10I/O28C4I/O24C0I/O45D10I/O40D0I/O51E6I/O53E10GNDI/O84G12I/O81G9I/O78G64I/O13B5I/O16B8I/O23B15VCCGNDVCCGNDVCCGNDVCCGNDVCCGNDI/O87G15I/O85G13I/O82G103I/O15B7I/O19B11I/O22B14I/O17B9I/O36C12I/O32C8I/O26C2I/O44D8I/O49E2I/O55E14I/O59F3I/O68F12TCKTMSI/O71F15I/O86G142I/O18B10I/O21B13TDII/O38C14I/O35C11I/O30C6I/O25C1I/O43D6I/O48E0I/O54E12I/O60F4I/O63F7I/O64F8I/O65F9I/O67F11I/O70F141I/O20B12NCI/O39C15I/O37C13I/O31C7I/O29C5I/O47D14I/O42D4I/O50E4I/O56F0I/O57F1I/O58F2I/O61F5I/O62F6I/O66F10I/O69F13ABCDEFGHJKLMNPRTI/O190GCLK3I/O188P12P8I/O176O8VCCGNDGNDVCCI/O98I4I/O100I8GNDI/O101I10I/O99I6I/O97I2I/O169O1GNDVCCVCCGNDI/O91H6I/O90H4VCCI/O89H2I/O96I0I/O88H0I/O185P2GNDVCCVCCGNDI/O75G3I/O74G2GNDI/O93H10I/O92H8GCLK1I/O103GCLK2I1416151413121110987654321PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O CellPAL Block17466G-04754ispMACH 4A Family

256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192)

Bottom View

256-Ball BGA

20ABCDEFGHJKGNDGNDI/O0XG6I/O1XE7I/O2XE0GNDI/O3XH6GNDI/O4XH0GNDI/O5A2I/O6A4GNDI/O7D2GNDI/O8B3I/O9B4I/O10B5GNDGND2019I/O11XF7I/O12XG7I/O13XG5I/O14XG3I/O15XG0I/O16XE1I/O17XE4I/O18XH5I/O19XH1CLK318GNDI/O28XF5VCCI/O29XG4I/O30XG1I/O31XE6I/O32XE5I/O33XE2I/O34XH4I/O35XH2I/O36A0I/O37A5I/O38D0I/O39D4I/O40D6I/O41B7I/O42B6VCCI/O43C6GND1817I/O44XF6I/O45XF3I/O46XF4VCCTDII/O47XG2VCCI/O48XE3I/O49XH7I/O50XH3I/O51A1I/O52A6I/O53D1VCCI/O54D7TCK16I/O58XC6I/O59XC7I/O60XF2VCC15GNDI/O64XC5I/O65XF1I/O66XF014I/O70XC2I/O71XC3I/O72XC4VCC13I/O76XD6I/O77XD7I/O78XC0I/O79XC112GNDI/O84XD5I/O85XD4I/O86XD311GNDI/O90XD2I/O91XD1I/O92XD010GNDI/O96XA0I/O97XA1I/O98XA29GNDI/O102XA3I/O103XA4I/O104XA78I/O108XA5I/O109XA6I/O110XB2I/O111XB37I/O116XB0I/O117XB1I/O118XB5VCC6GNDI/O122XB4I/O123O0I/O124O25I/O128XB7I/O129XB6I/O130O1VCC4I/O134O3I/O135O4I/O136O5VCCTDOI/O137N1VCC3GNDI/O148O6VCCI/O149N4I/O150N2I/O151N0I/O152P4I/O153P1I/O154M5I/O155M1I/O156L4I/O157L5I/O158I0I/O159I4I/O160K0I/O161K4I/O162K7VCCI/O163J6GND32GNDI/O164O7I/O165N7I/O166N5I/O167N3I/O168P5I/O169P3I/O170P0I/O171M4CLK21GNDGNDI/O181N6I/O182P7I/O183P6GNDI/O184M7GNDI/O185M3I/O186M2GNDI/O187L1GNDI/O188L2GNDI/O189I2I/O190I6I/O191I7GNDGND1ABCDEFGHJKPIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDO==========ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutI/O138P2I/O139M6I/O140M0I/O141L3LMNPRTCLK0I/O20A3I/O21A7I/O22D3I/O23D5I/O24B0I/O25B1I/O26B2I/O27C7GND19CLK1I/O172L0I/O173L7I/O174I1I/O175I3I/O176K1I/O177K2I/O178K3I/O179J7I/O180K62LMNPRTC7I/O CellPAL BlockI/O142L6I/O143I5VCCI/O144K5TMSUVWYVCCI/O55C5I/O56C3I/O57C417VCCI/O61C2I/O62F7I/O63F616I/O67C0I/O68C1I/O69F5GND15VCCI/O73F4I/O74F3I/O75F214I/O80F0I/O81F1I/O82E7I/O83E613I/O87E5I/O88E4I/O89E3GND12I/O93E2I/O94E1I/O95E0GND11I/O99H2I/O100H1I/O101H0GND10I/O105H5I/O106H4I/O107H3GND9I/O112G0I/O113G1I/O114H7I/O115H68VCCI/O119G4I/O120G3I/O121G27I/O125J1I/O126J0I/O127G5GND6VCCI/O131J2I/O132G7I/O133G65VCCI/O145J5I/O146J4I/O147J34UVWY17466G-046

ispMACH 4A Family55

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128)

Bottom View

256-Ball fpBGA

16ABCDEFGHJKLMNPRTTRSTI/O110N6I/O108N4NCI/O102M6I/O98M2NCI/O88L0I/O91L3NC15I/O117O5I/O111N7I/O109N5I/O104N0NCI/O103M7I/O96M0I10I/O92L4NC14I/O116O4I/O118O6NC13I/O113O1I/O115O3I/O119O7GND12I/O126P6I/O127P7I/O114O2GNDI/O105N1I/O100M4NCI/O89L1I/O95L7NCI/O83K3I/O67I3GNDI/O68I4I/O64I0I811I/O124P4I/O125P5I/O122P2VCCI/O106N2I/O99M3I/O97M1I/O90L2I/O94L6NC10I12I/O120P0I/O123P3GND9NC8NC7NC6CLK05I/O1A1I/O2A2I/O6A6GND4I/O5A5I/O8B0I/O5B7VCC3I/O7A7I/O11B3I/O14B6I/O9B1I/O20C4I/O16C0I/O26D2NC2I/O10B2I/O13B5TDII/O22C6I/O19C3I/O30D6I/O25D1NC1I/O12B4NCI/O23C7I/O21C5I/O31D7I/O29D5I2ABCDEFGHJKLMNPRTNCNCNCI1I/O4A4VCCI/O0A0I/O3A3I/O17C1I/O27D3I3NCNCI0TDOI/O107N3I/O101M5I11VCCGNDGNDVCCI13I/O112O0VCCCLK3I/O121P1GNDNCNCNCI/O18C2I/O28D4I/O24D0NCGNDGNDNCNCVCCVCCGNDVCCGNDI9I/O93L5NCI/O80K0I/O84K4TENBI/O78J6I/O72J0I/O70I6GNDGNDVCCVCCGNDVCCNCGNDGNDVCCVCCGNDGNDNCNCNCI/O32E0I/O33E1I/O34E2I/O37E5I/O38E6I/O42F2I/O45F5VCCVCCGNDGNDI/O59H3I/O58H2GNDVCCI/O61H5I/O48G0GNDNCNCVCCI4I/O35E3I/O44F4TCKNCI/O36E4I/O39E7I/O40F0I/O41F1I/O43F3I/O46F6NCI/O81K1I/O85K5I/O87K7I/O76J4I/O74J2NCI/O82K2I/O86K6I/O77J5I/O75J3I/O73J1GNDNCI/O65I1VCCI/O66I2I7NCNCNCI/O51G3VCCI/O63H7I/O60H4I/O57H1NCGNDGNDNCNCNCVCCVCCI/O79J7I/O71I7I/O69I5GNDVCCGNDI/O52G4I/O49G1I/O62H6GNDI/O55G7I/O53G5I/O50G2NCNCNCI6I/O56H0I5TMSI/O47F7I/O54G6NCNCNCCLK2NCNCCLK116151413121110987654321PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O CellPAL Blockm4a3.256.128_256bga56ispMACH 4A Family

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192)

Bottom View

256-Ball fpBGA

16ABCDEFGHJKLMNPRT15141312111098I/O1 A1I/O0A07I/O3 A3I/O5A5I/O6A6GNDI/O2A2I/O4 A4VCCGNDGNDVCCI/O69I5I/O80K0GNDI/O94L6I/O64I0I/O95L76CLK0I/O7A7I/O28D4VCCI/O24D0I/O27D3I/O17C1I/O43F3I/O38E6I/O33E1I/O60H4I/O83K3VCCI/O71I7I/O68I4I/O65I15I/O25D1I/O26D2I/O30D6GNDN/CI/O18C2I/O44F4I/O40F0I/O37E5I/O32E0I/O59H3I/O61H5GNDI/O84K4I/O81K1I/O70I64I/O29D5I/O8B0I/O15B7VCCGNDVCCGNDVCCGNDVCCGNDVCCGNDI/O87K7I/O85K5I/O82K23I/O31D7I/O11B3I/O14B6I/O9B1I/O20C4I/O16C0I/O42F2I/O36E4I/O57H1I/O63H7I/O51G3I/O76J4TCKTMSI/O79J7I/O86K62I/O10B2I/O13B5TDII/O22C6I/O19C3I/O46F6I/O41F1I/O35E3I/O56H0I/O62H6I/O52G4I/O55G7I/O72J0I/O73J1I/O75J3I/O78J61I/O12B4N/CI/O23C7I/O21C5I/O47F7I/O45F5I/O39E7I/O34E2I/O58H2I/O48G0I/O49G1I/O50G2I/O53G5I/O54G6I/O74J2I/O77J5I/O175I/O181I/O180I/O177I/O166I/O164I/O191I/O186FX7GX5GX4GX1EX6EX4HX7HX2I/O173I/O174I/O182I/O179I/O167I/O165I/O160I/O187FX5FX6GX6GX3EX7EX5EX0HX3I/O171I/O172FX3FX4I/O150I/O151CX6CX7I/O148CX4N/CN/CTDOI/O170FX2ABCDEFGHJKLMNPRTI/O183I/O178I/O162I/O163I/O189I/O184GX7GX2EX2EX3HX5HX0GNDVCCGNDVCCGNDGNDVCCGNDGNDVCCGNDI/O168FX0VCC169FX1GNDI/O190HX6VCCCLK3GNDI/O188HX4I/O144I/O149I/O147CX0CX5CX3I/O155I/O158I/O157DX3DX6DX5I/O152I/O154I/O153DX0DX2DX1I/O130I/O131I/O132AX2AX3AX4I/O135I/O136I/O137AX7BX0BX1I/O140I/O141I/O143BX4BX5BX7I/O112I/O113I/O115O0O1O3I/O116I/O117I/O119O4O5O7I/O146I/O145I/O176I/O161I/O185CX2CX1GX0EX1HX1I/O156I/O159DX4DX7I/O128I/O129AX0AX1I/O134I/O133AX6AX5I/O139I/O138BX3BX2I/O114I/O142O2BX6VCCGNDGNDVCCI/O98M2GNDVCCVCCGNDI/O91L3I/O90L2VCCI/O89L1I/O96M0I/O88L0GNDVCCVCCGNDI/O67I3I/O66I2GNDI/O93L5I/O92L4CLK1I/O123I/O121I/O100P3P1M4GNDVCCGNDI/O118I/O109I/O110I/O111I/O124I/O122I/O101O6N5N6N7P4P2M5I/O108I/O107I/O104I/O127I/O120I/O102N4N3N0P7P0M6I/O106I/O105I/O126I/O125I/O103N2N1P6P5M7CLK2I/O99M3I/O97M116151413121110987654321PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O CellPAL Blockm4a3.384.192_256bga

ispMACH 4A Family57

256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192)

Bottom View

256-Ball fpBGA

16ABCDEFGHJKL15141312111098I/O1A1I/O0A07I/O3A3I/O5A5I/O6A6GNDI/O2A2I/O4A4VCCGNDGNDVCCI/O77N5I/O80O0GNDI/O94P6I/O72N0I/O95P776CLK0I/O7A7I/O20C4VCCI/O16C0I/O19C3I/O33F1I/O43G3I/O30E6I/O25E1I/O68L4I/O83O3VCCI/O79N7I/O76N4I/O73N165I/O17C1I/O18C2I/O22C6GNDN/CI/O34F2I/O44G4I/O40G0I/O29E5I/O24E0I/O67L3I/O69L5GNDI/O84O4I/O81O1I/O78N654I/O21C5I/O8B0I/O15B7VCCGNDVCCGNDVCCGNDVCCGNDVCCGNDI/O87O7I/O85O5I/O82O243I/O21C7I/O11B3I/O14B6I/O9B1I/O36F4I/O32F0I/O42G2I/O28E4I/O65L1I/O71L7I/O51J3I/O60K4TCKTMSI/O63K7I/O86O632I/O10B2I/O13B5TDII/O38F6I/O35F3I/O46G6I/O41G1I/O27E3I/O64L0I/O70L6I/O52J4I/O55J7I/O56K0I/O57K1I/O59K3I/O62K621I/O12B4N/CI/O39F7I/O37F5I/O47G7I/O45G5I/O31E7I/O26E2I/O66L2I/O48J0I/O49J1I/O50J2I/O53J5I/O54J6I/O58K2I/O61K51ABCDEFGHJKLMNPRTI/O159I/O181I/O180I/O177I/O174I/O172I/O191I/O186KX7OX5OX4OX1NX6NX4PX7PX2I/O157I/O158I/O182I/O179I/O175I/O173I/O168I/O187KX5KX6OX6OX3NX7NX5NX0PX3I/O155I/O156KX3KX4I/O150I/O151JX6JX7I/O148JX4N/CN/CTDOI/O154KX2I/O183I/O178I/O170I/O171I/O189I/O184OX7OX2NX2NX3PX5PX0GNDVCCGNDVCCGNDGNDVCCGNDGNDVCCGNDVCCGNDVCCGNDI/O152I/O153I/O190KX0KX1PX6CLK3I/O188PX4I/O144I/O149I/O147JX0JX5JX3I/O163I/O166I/O165LX3LX6LX5I/O160I/O162I/O161LX0LX2LX1I/O122I/O123I/O124EX2EX3EX4I/O127I/O136I/O137EX7GX0GX1I/O140I/O141I/O143GX4GX5GX7I/O146I/O145I/O176I/O169I/O185JX2JX1OX0NX1PX1I/O164I/O167LX4LX7I/O120I/O121EX0EX1I/O126I/O125EX6EX5I/O139I/O138GX3GX2I/O130I/O142FX2GX6VCCGNDGNDVCCI/O98AX2GNDVCCVCCGNDI/O91P3I/O90P2VCCI/O89P1I/O96AX0I/O88P09GNDVCCVCCGNDI/O75N3I/O74N2GNDI/O93P5I/O92P4CLK18MI/O128 I/O129I/O131FX0FX1FX3NPRTI/O132I/O133I/O135FX4FX5FX7I/O115I/O113I/O100CX3CX1AX4GNDVCCGNDI/O134I/O109I/O110I/O111I/O116I/O114I/O101FX6BX5BX6BX7CX4CX2AX5I/O108I/O107I/O104I/O119I/O112I/O102BX4BX3BX0CX7CX0AX6I/O106I/O105I/O118I/O117I/O103BX2BX1CX6CX5AX71615141312CLK211I/O99AX3I/O97AX110PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O Cell PAL Blockm4a3.512.192_256bga58ispMACH 4A Family

388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256)

Bottom View

388-Ball fpBGA

22ABCDEFGHJKL2120191817161514131211I/O0A0I/O2A210I/O5A5CLK0I/O7A7I/O24D09I/O6A6I/O26D2I/O25D1VCC8I/O27D3I/O29D5I/O16C0I/O19C37I/O30D6I/O31D7I/O18C2I/O21C56I/O17C1I/O20C4I/O23C7VCC5I/O22C6I/O9B1I/O11B3I/O14B64I/O8B0I/O12B4I/O15B7GNDI/O45F5VCC3I/O10B2I/O13B5GNDI/O46F6I/O42F2I/O55G7I/O51G3I/O38E6I/O35E3I/O62H6I/O59H3I/O65I1I/O71I7I/O92L4I/O95L7I/O76J4I/O80K0I/O83K3I/O87K72N/CGNDI/O47F7I/O43F3I/O40F0I/O52G4I/O49G1I/O37E5I/O34E2I/O61H5I/O57H1I/O66I2I/O70I6I/O91L3I/O94L6I/O73J1I/O77J5I/O81K1I/O84K4TMS1GNDTDII/O44F4I/O41F1I/O54G6I/O50G2I/O39E7I/O36E4I/O32E0I/O60H4I/O56H0I/O64I0I/O68I4I/O90L2I/O93L5I/O72J0I/O75J3I/O79J7I/O82K2I/O85K5TCKGNDI/O243I/O240I/O241I/O236I/O231I/O228I/O226I/O255I/O251I/O248OX3OX0OX1NX4MX7MX4MX2PX7PX3PX0N/CGNDI/O245I/O242I/O238I/O234I/O232I/O229I/O224I/O253I/O249OX5OX2NX6NX2NX0MX5MX0PX5PX1ABCDEFGHJKLMNPRTUVWYAAABI/O213TDOKX5GNDI/O247I/O244I/O239I/O235I/O230I/O227CLK3I/O250I/O11OX7OX4NX7NX3MX6MX3PX2A1I/O3A3I/O210I/O212I/O215GNDI/O246VCCI/O237I/O233VCCI/O254VCCKX2KX4KX7OX6NX5NX1PX6I/O207I/O209I/O211I/O214JX7KX1KX3KX6I/O203I/O205I/O208VCCJX3JX5KX0I/O200I/O202I/O204I/O206JX0JX2JX4JX6I/O221I/O222I/O223I/O201LX5LX6LX7JX1I/O218I/O219I/O220VCCLX2LX3LX4I/O197I/O198I/O199I/O216IX5IX6IX7LX0I/O192I/O194I/O195I/O196IX0IX2IX3IX4VCCVCCN/CVCCN/CGNDN/CGNDGNDGNDGNDGNDGNDGNDGNDN/CI/O225I/O252MX1PX4GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDI/O4A4GNDGNDGNDGNDGNDGNDGNDGNDI/O28D4GNDGNDGNDGNDGNDGNDGNDGNDN/CGNDGNDGNDGNDGNDGNDGNDGNDN/CVCCN/CGNDGNDGNDGNDGNDGNDN/CVCCVCCVCCN/CI/O33E1I/O58H2I/O69I5I/O89L1N/CVCCVCCI/O53G5I/O48G0VCCI/O63H7VCCI/O67I3I/O88L0VCCI/O74J2I/O78J6VCCI/O86K6I/O217GNDLX1I/O193GNDIX1I/O186GNDHX2I/O162GNDEX2N/CVCCVCCGNDN/CVCCI/O185I/O187VCCMI/O184HX0HX1HX3NPRTUVI/O188I/O189I/O191I/O190HX4HX5HX7HX6I/O160I/O161I/O163VCCEX0EX1EX3I/O164I/O165I/O166I/O177EX4EX5EX6GX1I/O167I/O176I/O179I/O181EX7GX0GX3GX5I/O178I/O180I/O183VCCGX2GX4GX7I/O182GX6N/CI/O169I/O172FX1FX4I/O152I/O131I/O122I/O98DX0AX3P2M2I/O170I/O173GNDI/O143VCCI/O150I/O145VCCI/O153I/O123VCCWI/O168FX0FX2FX5BX7CX6CX1DX1P3I/O96M0VCCI/O104I/O111VCCI/O119GNDN0N7O7YI/O171I/O174GNDI/O141I/O138I/O136I/O147I/O158I/O156CLK2I/O132I/O121I/O125I/O99I/O101I/O106I/O110I/O115I/O118GNDFX3FX6BX5BX2BX0CX3DX6DX4AX4P1P5M3M5N2N6O3O6GNDI/O142I/O140I/O151I/O149I/O144I/O157I/O154I/O134I/O130I/O128CLK1I/O127I/O100I/O103I/O108I/O109I/O113I/O116GNDAAI/O175FX7BX6BX4CX7CX5CX0DX5DX2AX6AX2AX0P7M4M7N4N5O1O4ABGNDN/CI/O139I/O137I/O148I/O146I/O159I/O155I/O135I/O133I/O129I/O120I/O124I/O126I/O97I/O102I/O105I/O107I/O112I/O114I/O117GNDBX3BX1CX4CX2DX7DX3AX7AX5AX1P0P4P6M1M6N1N3O0O2O522212019181716151413121110987654321PIN DESIGNATIONSCLKGNDII/ON/CVCCTDITCKTMSTDOTRSTENABLE============ClockGroundInputInput/OutputNo ConnectSupply VoltageTest Data InTest ClockTest Mode SelectTest Data OutTest ResetProgramC7I/O CellPAL Blockm4a3.512.256_388bgaispMACH 4A Family59

ispMACH 4A PRODUCT ORDERING INFORMATION

ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V

Lattice programmable logic products are available with several ordering options. The order number (Valid Combination)is formed by a combination of:

M4A3-256/128

-7

Y

C

FAMILY TYPE

M4A3-=ispMACH 4A Family Low Voltage Advanced

Feature (3.3-V VCC)

M4A5-=ispMACH 4A Family Advanced Feature (5-V VCC)MACROCELL DENSITY

32=32 Macrocells19264=64 Macrocells25696=96 Macrocells384128=128 Macrocells512

48

=48-pin TQFP for

M4A3-32/32 or M4A3-64/32 M4A5-32/32 or M4A5-64/32

====192 Macrocells256 Macrocells384 Macrocells512 Macrocells

OPERATING CONDITIONSC=Commercial (0°C to +70°C)I=Industrial (-40°C to +85°C)PACKAGE TYPEA=Ball Grid Array (BGA)J=Plastic Leaded Chip Carrier

(PLCC)

V=Thin Quad Flat Pack (TQFP)Y=Plastic Quad Flat Pack (PQFP)FA=Fine-pitch Ball Grid Array

(fpBGA)

CA=Chip-array Ball Grid Array

(caBGA)SPEED-5=5.0 ns tPD-55=5.5 ns tPD-6=6.0 ns tPD-65=6.5 ns tPD-7=7.5 ns tPD-10=10 ns tPD-12=12 ns tPD-14=14 ns tPD

I/Os

/32 /48 /64/96/128/160/192/256

========32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP48 I/Os in 100-pin TQFP

64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA96 I/Os in 144-pin TQFP or 144-ball fpBGA

128 I/Os in 208-pin PQFP, 256-ball BGA or 256-ball fpBGA160 I/Os in 208-pin PQFP

192 I/Os in 256-ball BGA or 256-ball fpBGA256 I/Os in 388-ball fpBGA

3.3V Commercial Combinations

M4A3-32/32-5, -7, -10JC, VC, VC48M4A3-64/32JC, VC, VC48M4A3-64/64VC

-55, -7, -10

M4A3-96/48VCM4A3-128/64YC, VC, CACM4A3-192/96-6, -7, -10VC, FACM4A3-256/128-55, -65, -7, -10YC, AC, FAC

1M4A3-256/160YC

-7, -101M4A3-256/192FAC

M4A3-384/160YC

-65, -10, -12

M4A3-384/192AC, FACM4A3-512/160YCM4A3-512/192-7, -10, -12FACM4A3-512/256FAC1.Contact Factory for 6.5ns availability

M4A3-32/32

M4A3-64/32M4A3-64/64M4A3-96/48M4A3-128/64M4A3-192/96M4A3-256/128M4A3-256/160M4A3-256/192M4A3-384/160M4A3-384/192M4A3-512/160M4A3-512/192M4A3-512/256

3.3V Industrial Combinations

JI, VI, VI48JI, VI, VI48VI-7, -10, -12

VI

YI, VI, CAIVI, FAI

-7, -10, -12

YI, AI, FAIYI

-10, -12

FAIYIAI, FAIYI-10, -12, -14

FAIFAI

60ispMACH 4A Family

5V Commercial Combinations

M4A5-32/32-5, -7, -10, JC, VC, VC48M4A5-64/32JC, VC, VC48M4A5-96/48-55, -7, -10VCM4A5-128/64YC, VCM4A5-192/96-6, -7, -10VCM4A5-256/128-65, -7, -10YC, AC

M4A5-32/32

M4A5-64/32M4A5-96/48M4A5-128/64M4A5-192/96M4A5-256/128

5V Industrial Combinations

-7, -10, -12JI, VI, VI48

JI, VI, VI48

-7, -10, -12VI

YI, VI

-7, -10, -12VI-10, -12YI, AI

Most ispMACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4A3-256/128-7YC-10YI

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to

confirm availability of specific valid combinations and to check on newly released combinations.

Copyright © 2000 Lattice Semiconductor. All rights reserved.

ispMACH 4A Family61

62ispMACH 4A Family