High-speed compression architecture for memory

专利名称：High-speed compression architecture for

memory

发明人：Jeffrey T. Feng申请号：US12625034申请日：20091124公开号：US08134885B2公开日：20120313

专利附图：

摘要：Memory design techniques are disclosed that provide a high compression ratioat no loss in speed. The techniques can be embodied, for instance, in heterojunctionbipolar transistor (HBT) based ROMs. By embedding compression logic (e.g., XOR)

functionality directly into the address decoders and sense amplifiers of the memorydevice, a high compression ratio is achieved at no loss in speed. For example, the logic-based compression functionality can be directly implemented into the buffers that formthe address decoder as well as the sense amplifiers.

申请人：Jeffrey T. Feng

地址：Cambridge MA US

国籍：US

代理机构：Finch & Maloney, PLLC

代理人：Neil F. Maloney

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