ICS1526资料

Integrated Circuit Systems

Preliminary Data Sheet

ICS1526

Video Clock Synthesizer

General Description

The ICS1526 is a low-cost, high-performance

frequency generator. It is suited to general purpose phase controlled clock synthesis as well as

line-locked and genlocked high-resolution video applications. Using ICS’s advanced low-voltage CMOS mixed-mode technology, the ICS1526 is an effective clock synthesizer that supports video projectors and displays at resolutions from VGA to beyond XGA.

The ICS1526 offers single-ended clock outputs to 200 MHz. The HSYNC_out, and VSYNC_out pins provide the regenerated versions of the HSYNC and VSYNC inputs synchronous to the CLK output.

The advanced PLL uses its internal programmable feedback divider. The device is programmed by a standard I2C-bus™ serial interface and is available in a TSSOP16 package.

Features

• Lead-free packaging (Pb-free)

• Low jitter (typical 27 ps short term jitter)• Wide input frequency range

• 8 kHz to 100 MHz

• LVCMOS single-ended clock outputs

• Up to 200 MHz

• Uses 3.3 V power supply

• 5 Volt tolerant Inputs (HSYNC, VSYNC)

• Coast (ignore HSYNC) capability via VSYNC pin• Industry standard I2C-bus programming interface • PLL Lock detection via I2C or LOCK output pin• 16-pin TSSOP package

Applications

• Frequency synthesis

• LCD monitors, video projectors and plasma displays• Genlocking multiple video subsystems

ICS1526 Functional Diagram

Pin Configuration (16-pin TSSOP)

OSCHSYNCVSYNCI2CHSYNC_outICS1526VSYNC_outCLKLOCKVSSDSDASCLVSYNCHSYNCVDDAVSSAOSC12345678161514131211109VDDDVSSQVSYNC_outVDDQCLKHSYNC_outLOCKI2CADRMDS 1526 I

ICS reserves the right to make changes in the preliminary device data identified in this publication without notice. ICS advises its customers to obtain the latest version of all device data to verify that information

being relied upon is current and accurate.

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Section 1Overview

Section 1Overview

The ICS1526 has the ability to operate in line-locked mode with the HSYNC input.

The ICS1526 is a user-programmable,

high-performance general purpose clock generator. It is intended for graphics system line-locked and

genlocked applications and provides the clock signals required by high-performance analog-to-digital converters.

1.1Phase-Locked Loop

The phase-locked loop has a very wide input frequency range (8 kHz to 100 MHz). Not only is the ICS1526 an excellent, general purpose clock synthesizer, but it is also capable of line-locked operation. Refer to the block diagram below.

Figure 1-1Simplified Block Diagram

OSCHSYNCDivider3..129PFDCPVCOVCOD2,4,8,16CLKFD12..4103Flip-flopVSYNCFlip-flopHSYNC_outVSYNC_outNote: Polarity controls and other circuit elements are not shown in above diagram for simplicityThe heart of the ICS1526 is a voltage controlled

oscillator (VCO). The VCOs speed is controlled by the voltage on the loop filter. This voltage will be described later in this section.

The VCOs clock output is first passed through the VCO Divider (VCOD). The VCOD allows the VCO to operate at higher speeds than the required output clock. NOTE: Under normal, locked operation the VCOD has no effect on the speed of the output clocks, just the VCO frequency.

The output of the VCOD is the full speed output frequency seen on the CLK. This clock is then sent through the 12-bit internal Feedback Divider (FD). The feedback divider controls how many clocks are seen during every cycle of the input reference.

The Phase Frequency Detector (PFD) then compares the feedback to the input and controls the filter voltage by enabling and disabling the charge pump. The

charge pump has programmable current drive and will source and sink current as appropriate to keep the input and the clock output aligned.

MDS 1526 I

2

The input HSYNC and VSYNC can be conditioned by a high-performance Schmitt-trigger by sharpening the rising/falling edge.

The HSYNC_out and VSYNC_out signals are aligned with the output clock (CLK) via a set of flip flops.

1.2Output Drivers and Logic Inputs

The ICS1526 uses low-voltage TTL (LVTTL) inputs and LVCMOS outputs, operating at the 3.3 V supply voltage. The LVTTL inputs are 5 V tolerant. The LVCMOS drive resistive terminations or transmission lines.

1.3Automatic Power-On Reset Detection

The ICS1526 has automatic power-on reset detection (POR) circuitry and it resets itself if the supply voltage drops below threshold values. No external connection to a reset signal is required.

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Section 1Overview

1.4I2C Bus Serial Interface

The ICS1526 uses a 5 volt tolerant, industry-standard I2C-bus serial interface that runs at either low speed (100 kHz) or high speed (400 kHz). The interface uses 12 word addresses for control and status: one write-only, eight read/write, and three read-only addresses.

Two ICS1526 devices can sit on the same I2C bus, each selected by the Master according to the state of the I2CADR pin. The 7-bit device address is 0100110 (binary) when I2CADR is low. The device address is 0100111 (binary) when I2CADR is high. See Section 4, “Programming”

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Section 2Pin Descriptions

Section 2Pin Descriptions

TYPEPOWERIN/OUTINININPOWERPOWERININLVCMOS OUTLVCMOS OUTLVCMOS OUTPOWERLVCMOS OUTPOWERPOWER

DESCRIPTIONDigital groundSerial dataSerial clockVertical syncHorizontal syncAnalog supplyAnalog groundOscillator

I2C device addressLock

HSYNC outputPixel clock outputOutput driver supplyVSYNC outputOutput driver groundDigital supply

Clock input to PLLPower for analog circuitryGround for analog circuitry

Input from crystal oscillator packageChip I2C address selectPLL Lock detect

Schmitt-trigger filtered HSYNC realigned with the output pixel clockLVCMOS driver for full speed clockPower for output drivers

Schmitt-trigger filtered VSYNC

realigned with the output pixel clockGround for output driversPower for digital sections

1 & 2

I2C-bus I2C-bus

111 & 21 & 2

COMMENTS

Notes

Table 2-1ICS1526 Pin Descriptions

PIN NO.PIN NAME

123456710111213141516

VSSDSDASCLVSYNCHSYNCVDDAVSSAOSCI2CADRLOCKHSYNC_out CLK VDDQVSYNC_outVSSQVDDD

Notes: 1. These LVTTL inputs are 5 V tolerant.

2. Connect to ground if unused.

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Section 3Register map summary

Section 3

Word Address00h

Register map summary

Reset Value10

NameInput Control

AccessR / W

Bit NameCPenVSYNC_Pol

Bit # 01

Description

Charge Pump Enable

0=External Enable via VSYNC, 1=Always EnabledVSYNC Polarity (Charge Pump Enable)Requires 00h:0=0

0=Coast (charge pump disabled) while VSYNC low,1=Coast (charge pump disabled) while VSYNC highHSYNC Polarity

0=Rising Edge, 1=Falling EdgeReserved

Part requires a 0 for correct operationReserved

Enable PLL Lock Output 0=Disable, 1=EnableReserved

ICP (Charge Pump Current)

Bit 2,1,0 = {000 =1 µA, 001 = 2 µA, 010 = 4 µA... 110 = µA, 111 = 128 µA}Reserved

VCO Divider

Bit 5,4 = {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}Reserved

Feedback Divider LSBs (bits 0-7)

HSYNC_PolReservedReservedReservedEnPLSReserved

01h

Loop Control*

R / W

ICP0-2

2345670-2

000010

ReservedVCOD0-1Reserved

02h

FdBk Div

0*FdBk Div

1*

R / W

FBD0-7

34-56-70-7

03hR / WFBD8-110-3

Feedback Divider MSBs (bits 8-11)Divider setting = 12-bit word + 8Minimum 12 = 000000000100Maximum 4103 =111111111111Reserved010000

Reserved

Schmitt-trigger control

0=Schmitt-trigger, 1=No Schmitt-triggerMetal Mask Revision NumberReserved

Output Enable for CLK, HSYNC_out, VSYNC_out0=High Impedance (disabled), 1=EnabledReserved

Reserved

04h05h

ReservedSchmitt-trigger*

R / W

ReservedSchmitt controlMetal_Rev

06h

Output Enables

R / W

ReservedOEReserved

4-70-701-7012-7

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Word Address07h

Reset Value0

Section 3Register map summary

NameOsc_Div

AccessR / W

Bit NameOsc_Div 0-6

Bit # 0-6

Description

Osc Divider modulus

Minimum 3 =0000001 binary, Maximum 129 = 1111111 binaryDivider setting = 7-bit word + 2

Input Select

0=HSYNC Input, 1=OSC Input

OSC input clock must be present to select OSC inputWriting 5Ah resets PLL and commits values written to word addresses 01h-03h and 05hReservedReserved

In-Sel70

08hResetWritePLL0-7x

09-0Fh10h11h12h

ReservedChip VerChip RevRd_Reg

ReadReadReadRead

ReservedReservedChip RevReservedPLL_LockReserved

0-70-70-7012-7

01N/AN/A0

ReservedReserved

PLL Lock Status

0=Unlocked, 1=LockedReserved

*.Written values to these registers do not take effect immediately, but require a commit via register 08h

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Section 4Programming

Section 4Programming

4.1Industry-Standard I2C Serial Bus: Data Format

ICS1526 Data Format for I2C 2-Wire Serial Bus

Data (0)ACKACK...Data (n)ASCTKOPFigure 4-1

Single/multiple register write (page write)Device addressWord addressS010011B0ATCAKRTSingle/multiple register readDevice addressS010011B0ATCAKRTSequential single/multiple register readDevice addressS010011B1ATCAKRTMaster drives lineData (0)Word addressDevice addressAS010011B1ACTCKAKRTData (0)ACK...Data (n)NOACKSTOPData (n)ACK...NOACKSTOPSlave drives lineNotes:

The ICS1526 uses 16-byte pages (00h-0Fh is the first page, 10h-1Fh is the second page). Writing or reading beyond the end of page yields undefined results.

The ICS1526 has a device address of 010011B, where B is the state of the I2CADR pin.

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Section 5AC/DC Operating Conditions

Section 5AC/DC Operating Conditions

5.1Absolute Maximum Ratings

Table 5-1 lists absolute maximum ratings for the ICS1526. Stresses above these ratings can cause permanent damage to the device. These ratings, which are standard values for ICS commercially rated parts, are stress rat-ings only. Functional operation of the ICS1526 at these or any other conditions above those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Table 5-1ICS1526 Absolute Maximum Ratings

Item

VDD, VDDA, VDDQ (measured to VSS)*Digital Inputs Analog InputsAnalog Outputs Digital Outputs Storage TemperatureJunction TemperatureSoldering TemperatureESD Susceptibility*

Rating4.3 V

VSS –0.3 V to 5.5 VVSS -0.3 V to 6.0 V

VSSA –0.3 V to VDDA +0.3 VVSSQ –0.3 V to VDDQ +0.3 V–65°C to +150°C 125°C260°C> 2 KV**

*.Measured with respect to VSS. During normal operations, the VDD supply voltage for the ICS1526 must remain within the recommended operating conditions.

**.Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.

Table 5-2Environmental Conditions

Parameter

Ambient Operating TemperaturePower Supply Voltage

Table 5-3DC Characteristics

Min.

0+3.0

Typ.

–+3.3

Max.

+70+3.6

Units

° CV

Parameter

Digital Supply CurrentOutput Driver Supply CurrentAnalog Supply CurrentPower consumptionPower-On-Reset (POR) Threshold

Symbol

IDDDIDDQIDDA

Conditions

VDDD = 3.6 VVDDD = 3.6 VNo drivers enabledVDDA = 3.6 V

VSS

Min.

---

Max.

25653001.8

Units

mAmAmAmWV

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Section 5AC/DC Operating Conditions

ParameterSymbol

fVCOKfOSCfHSYNCfVSYNCVIHVIL

Min.

40

TypicalMax.

400

Units

MHzMHz/V

Notes

General

VCO FrequencyVCO Gain

165

0.028301.7VSS - 0.30.2

VIHVILVIHVILVOLVOH

2VSS - 0.3

2VSS - 0.3

10010,0001205.51.10.85.50.8VDD+0.30.80.46.0

AC Inputs

OSC Input FrequencyHSYNC Input FrequencyVSYNC Input FrequencyInput High VoltageInput Low VoltageInput Hysteresis

MHzkHzHzVVVVVVVVV

IOUT = 3 mADetermined by external Rset resistor

VDDD = 3.3 V

2

30 kHz input to 50 MHz outputHSYNC in to CLK out

1

Schmitt trigger active

Analog Input (HSYNC/VSYNC)

SDA, SCL, OSC Digital Inputs

Input High Voltage

Input Low Voltage

I2CADDR Digital InputInput High VoltageInput Low Voltage

SDA Digital Output

SDA Output Low VoltageSDA Output High Voltage

LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK)

Output FrequencyDuty CycleJitter, STJ, RMSJitter, STJ, pk-pkJitter, Input-OutputHSYNC to HSYNC_out propagation delay (without Schmitt trigger)HSYNC to HSYNC_out propagation delay (with Schmitt-trigger)CLK to HSYNC_out/ VSYNC_out skewClock/ HSYNC_out/ VSYNC_out

Transition Time - Rise

TCR

1.0

FsSDCSTJSTJIOJ

2.5

500.0270.2002.5002

920055

MHz%nsnsnsns

610ns1

1.01.5

nsns

2

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Section 5AC/DC Operating Conditions

Parameter

Clock/ HSYNC_out/ VSYNC_out

Transition Time - FallLOCK Transition Time - RiseLOCK Transition Time - Fall

Symbol

TCF

Min.Typical

1.0

Max.

1.5

Units

ns

Notes

2

TLRTLF

3.02.0

nsns

22

Note 1—Measured between chosen edge of HSYNC (00h:2) and rising edge of outputNote 2—Measured at 110 MHz, 3.3 VDC, 25oC, 15 pF, unterminated

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Section 6Package Outline and Package Dimensions

Section 6Package Outline and Package Dimensions

16-pin TSSOP 4.40 mm body, 0.65 mm pitch

Package dimensions are kept current with JEDEC Publication No. 95

16MillimetersSymbolMinMaxInchesMinMaxE1INDEXAREAE1 2DAA1A2bCDEE1eLαaaa--1.200.050.150.801.050.190.300.090.204.905.16.40 BASIC4.304.500.65 Basic0.450.750°8°--0.10--0.0470.0020.0060.0320.0410.0070.0120.00350.0080.1930.2010.252 BASIC0.1690.1770.0256 Basic0.0180.0300°8°--0.004A2A1Ac- C -ebSEATINGPLANE aaaCLSection 7Ordering Information

Marking

1526GLF1526GLF

Part / Order Number

ICS1526GLFICS1526GLFTR

Shipping Packaging

TubesTape & Reel

Package

16-pin TSSOP16-pin TSSOP

Temperature

0 to +70° C0 to +70° C

“LF” denotes Pb (lead) free package.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

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