专利名称：Methods and apparatus for estimating a
position of a stuck-at defect in a scan chainof a device under test
发明人：Phillip D. Burlison,John K. Frediani申请号：US12074015申请日：20080228公开号：US08127186B2公开日：20120228
专利附图：
摘要：As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated inreal-time for the existence of a logic condition. A reference to a portion of the scan
pattern that is currently being evaluated is maintained. Upon identifying the existence ofthe logic condition when the reference has a predetermined relationship to a storedvalue, the stored value is overwritten using the reference. The stored value is then usedto estimate the position of a stuck-at defect in the scan chain.
申请人：Phillip D. Burlison,John K. Frediani
地址：Morgan Hill CA US,Corralitos CA US
国籍：US,US
代理机构：Holland & Hart, LLP
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