Area efficient memory architecture with decoder se

专利名称：Area efficient memory architecture with

decoder self test and debug capability

发明人：Prashant Dubey申请号：US11437420申请日：20060518公开号：US08046655B2公开日：20111025

专利附图：

摘要：An integrated test device reduces external wiring congestion to a memory. Theintegrated test device provides for separate decoder testing and debugging to findspecific errors in the memory. The device also helps in reducing the complexity of the

test of external BIST. Furthermore, the number of clock cycles required for the decodertesting for an N-address memory is reduced from 4N cycles to N clock cycles.Additionally, the access time for the memory is reduced as the test device is used as apipelining device in normal operation mode.

申请人：Prashant Dubey

地址：Ghaziabad IN

国籍：IN

代理机构：Seed IP Law Group PLLC

代理人：Lisa K. Jorgenson,E. Russell Tarleton

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