METHOD AND APPARATUS FOR SYNCHRONIZING PROCESSORS

专利名称：METHOD AND APPARATUS FOR

SYNCHRONIZING PROCESSORS IN AHARDWARE EMULATION SYSTEM

发明人：BERSHTEYN, Mikhail,BERGHORN,

Charles,POPLACK, Mitchell G.

申请号：EP07777334.9申请日：20070530公开号：EP2033091A1公开日：20090311

摘要：A method, apparatus and method for compiling a hardware design forperforming hardware emulation using synchronized processors is described. Theapparatus comprises a plurality of processors defining a processor group for evaluatingdata regarding a hardware design and a synchronizer for synchronizing the operation ofthe processor group while emulating at least a portion of the hardware design. Themethod comprises providing a synchronization signal to a plurality of processors defininga processor group for evaluating data regarding a hardware design, receiving a readysignal from the processor group, and providing an execution signal to the processorgroup, where the execution signal causes the processor group to evaluate a submodel.The method for compiling the hardware design comprises converting at least one high-level construct into a sequence of operations and identifying a sequence of operationsthat comprise at least one conditional submodel.

申请人：Cadence Design Systems, Inc.

地址：2655 Seely Avenue San Jose, CA 95134 US

国籍：US

代理机构：Hess, Peter K. G.

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