METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING

专利名称：METHOD AND APPARATUS FOR ADAPTIVE

VOLTAGE SCALING TO ELIMINATE DELAYVARIATION OF WHOLE DESIGN

发明人：Mei-Li Yu,Ying-Chieh Chen,Yu-Lan Lo,Hsin-Chang Lin,Shu-Yi Kao

申请号：US16355837申请日：20190317

公开号：US20190384868A1公开日：20191219

专利附图：

摘要：A method and apparatus for adaptive voltage scaling to eliminate delay

variation of a whole design are provided. The method may include: reading a circuitsimulation netlist file, a circuit design database, and a path list; building a delay variationdatabase of each minimum unit within multiple minimum units of the whole design undervarious voltage levels according to the circuit design database; utilizing an initial voltagelevel to be a voltage level of a driving voltage of the whole design to apply the initialvoltage level to the whole design, and performing static timing analysis (STA) on thewhole design, to determine whether any timing violation path exists in the path list; andselectively adjusting the voltage level of the driving voltage and re-performing the STAuntil no timing violation path exists.

申请人：Realtek Semiconductor Corp.

地址：HsinChu TW

国籍：TW

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