专利名称：Simplified high reliability gate oxide process发明人：Paul A. Fearon,Todd P. Thibeault申请号：US07/905772申请日：19920629公开号：US05290718A公开日：19940301
摘要：A new IC wafer fabrication process provides an improved CMOS active stripmask, etch, V.sub.T adjust, and gate oxide grow sequence particularly applicable forpreparation of CMOS transistors in BICMOS wafers. The new gate oxide process reducesthe number of process steps and thermal cycles, increases the reliability of the gateoxide layer, and substantially reduces differential stress and thermal stress relatedstructural silicon defects in the epitaxial silicon. The process proceeds by forming aphotoresist CMOS active strip mask exposing CMOS transistor active areas, etching andremoving the CVD nitride layer over the CMOS transistor active areas, and leaving theEPIOX layer. Further steps include introducing dopant material through the EPIOX layerinto the EPI layer of CMOS transistor active areas with the photoresist active strip mask inplace and adjusting the threshold voltage V.sub.T of the CMOS transistors. The inventionproceeds by stripping the EPIOX layer over the CMOS transistor active areas withoutgrowing a sacrificial oxide SACOX layer, and then removing the photoresist CMOS activestrip mask. This step is followed by growing a gate oxide layer over the CMOS transistoractive areas using a wet oxide grow process at relatively lower temperature than a dryoxide grow process. Other steps of the invention include forming the combined
thicknesses of the CVDSIN and EPIOX layers to provide the control screen necessary for
controlling the subsequent base implant to maintain the desired &bgr; specification forbipolar transistors. The layers are formed in a thickness ratio CVDSIN/EPIOX in the rangeof approximately 5/3 or smaller to achieve the desired reduction in silicon defects andincrease in current leakage test yield.
申请人：NATIONAL SEMICONDUCTOR CORPORATION
代理人：Daniel H. Kane,Richard C. Calderwood,Stephen R. Robinson
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