ADC10154资料

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ReferenceNovember1999

ADC10154/ADC10158

10-BitPlusSign4µsADCswith4-or8-ChannelMUX,Track/HoldandReference

GeneralDescription

Features

TheADC10154andADC10158areCMOS10-bitplussignn4-or8-channelconfigurablemultiplexersuccessiveapproximationA/Dconverterswithversatileana-nAnaloginputtrack/holdfunction

loginputmultiplexers,track/holdfunctionanda2.5Vn0Vto5Vanaloginputrangewithsingle+5Vpowerband-gapreference.The4-channelor8-channelmultiplex-supply

erscanbesoftwareconfiguredforsingle-ended,differentialorpseudo-differentialmodesofoperation.

n−5Vto+5Vanaloginputvoltagerangewith±5Vsupplies

Theinputtrack/holdisimplementedusingacapacitivearraynFullytestedinunipolar(single+5Vsupply)andbipolarandsampled-datacomparator.

(dual±5Vsupplies)operation

Resolutioncanbeprogrammedtobe8-bit,8-bitplussign,nProgrammableresolution/speedandoutputdataformat10-bitor10-bitplussign.Lower-resolutionconversionscannRatiometricorAbsolutevoltagereferenceoperationbeperformedfaster.

nNozeroorfullscaleadjustmentrequiredThevariableresolutionoutputdatawordisreadintwobytes,nNomissingcodesovertemperatureandcanbeformattedleftjustifiedorrightjustified,highbytefirst.

nEasymicroprocessorinterface

Applications

KeySpecifications

nProcesscontrolnResolution

10-bitplussignnInstrumentationnIntegrallinearityerror

±1LSB(max)nTestequipment

nUnipolarpowerdissipation

33mW(max)nConversiontime(10-bit+sign)4.4µs(max)nConversiontime(8-bit)

3.2µs(max)

nSamplingrate(10-bit+sign)166kHznSamplingrate(8-bit)207kHz

Band-gapreference

2.5V±2.0%(max)

ADC10158SimplifiedBlockDiagram

DS011225-1

TRI-STATE®isaregisteredtrademarkofNationalSemiconductorCorporation.

ADC10154/ADC1015810-BitPlusSign4µsADCswith4-or8-ChannelMUX,Track/Holdand元器件交易网www.cecb2b.com

ConnectionDiagrams

Dual-in-LineandSOPackages

DS011225-2

TopView

OrderNumberADC10154NSPackageNumberM24B

PinDescriptions

AV+Thisisthepositiveanalogsupply.Thispinshouldbebypassedwitha0.1µFceramicca-pacitoranda10µFtantalumcapacitortothesystemanalogground.

Thisisthepositivedigitalsupply.Thissupplypinalsoneedstobebypassedwith0.1µFce-ramicand10µFtantalumcapacitorstothesystemdigitalground.AV+andDV+shouldbebypassedseparatelyandtiedtosamepowersupply.

Thisisthedigitalground.Alllogiclevelsarere-ferredtothisground.

Thisisthenegativeanalogsupply.Forunipolaroperationthispinmaybetiedtothesystemanaloggroundortoanegativesupplysource.ItshouldnotgoaboveDGNDbymorethan50mV.Whenbipolaroperationisrequired,thevoltageonthispinwilllimittheanaloginput’snegativevoltagelevel.Inbipolaroperationthissupplypinneedstobebypassedwith0.1µFceramicand10µFtantalumcapacitorstothesystemanalogground.

Thesearethepositiveandnegativereferenceinputs.ThevoltagedifferencebetweenVREF+andVREF−willsettheanaloginputvoltagespan.

Thisistheinternalband-gapvoltagereferenceoutput.Forproperoperationofthevoltageref-erence,thispinneedstobebypassedwitha330µFtantalumorelectrolyticcapacitor.Thisisthechipselectinput.WhenalogiclowisappliedtothispintheWRandRDpinsareenabled.

Thisisthereadcontrolinput.Whenalogiclowisappliedtothispinthedigitaloutputsareen-abledandtheINToutputisresethigh.Thisisthewritecontrolinput.Therisingedgeofthesignalappliedtothispinselectsthemul-tiplexerchannelandinitiatesaconversion.

WRDV+INTDGNDV−VREF+,VREF−VREFOut

CSThisistheinterruptoutput.Alogiclowatthisoutputindicatesthecompletionofaconver-sion.

CLKThisistheclockinput.Theclockfrequencydi-rectlycontrolsthedurationoftheconversion

time(forexample,inthe10-bitbipolarmodetC=22/fCLK)andtheacquisitiontime(tA=6/fCLK).

DB0(MA0)Thesearethedigitaldatainputs/outputs.DB0–DB7(L/R)istheleastsignificantbitofthedigitaloutput

word;DB7isthemostsignificantbitinthedigi-taloutputword(seetheOutputDataConfigu-rationtable).MA0throughMA4arethedigitalinputsforthemultiplexerchannelselection(seetheMultiplexerAddressingtables).U/S(Unsigned/Signed),8/10,(8/10-bitresolution)andL/R(Left/Rightjustification)arethedigitalinputbitsthatsettheA/D’soutputwordformatandresolution(seetheOutputDataConfigura-tiontable).Theconversiontimeismodifiedbythechosenresolution(seeElectricalACChar-acteristicstable).Thelowertheresolution,thefastertheconversionwillbe.

CH0–CH7Thesearetheanaloginputmultiplexerchan-nels.Theycanbeconfiguredassingle-endedinputs,differentialinputpairs,orpseudo-differentialinputs(seetheMultiplexerAddressingtablesfortheinputpolarityassignments).

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ADC10154/ADC10158AbsoluteMaximumRatings(Notes1,3)

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.PositiveSupplyVoltage(V+=AV+=DV+)

NegativeSupplyVoltage(V−)TotalSupplyVoltage(V+−V−)TotalReferenceVoltage(VREF+−VREF−)VoltageatInputsandOutputs

InputCurrentatAnyPin(Note4)PackageInputCurrent(Note4)PackageDissipationatTA=25˚C(Note5)

ESDSusceptibility(Note6)SolderingInformationNPackages(10Sec)JPackages(10Sec)SOPackage(Note7):VaporPhase(60Sec)Infrared(15Sec)

6.5V−6.5V13V6.6V

V−0.3VtoV+0.3V

±5mA±20mA

500mW2000V260˚C300˚C215˚C220˚C

−+StorageTemperatureCeramicDIPPackages

PlasticDIPandSOPackages

−65˚Cto+150˚C−40˚Cto+150˚C

OperatingRatings(Notes2,3)

TemperatureRangeADC10154CIWM,ADC10158CIN,ADC10158CIWMPositiveSupplyVoltage

(V+=AV+=DV+)UnipolarNegativeSupplyVoltage(V−)

BipolarNegativeSupplyVoltage(V−)+V−V−VREF+VREF−VREF(VREF+−VREF−)

TMIN≤TA≤TMAX−40˚C≤TA≤+85˚C

4.5VDCto5.5VDCDGND

AV++0.05VDCAV++0.05VDC−4.5Vto−5.5V

11V

−toV−0.05VDCtoV−−0.05VDC0.5VDCtoV+ElectricalCharacteristics

ThefollowingspecificationsapplyforV+=AV+=DV+=+5.0VDC,VREF+=5.000VDC,VREF−=GND,V−=GNDforunipo-laroperationorV−=−5.0VDCforbipolaroperation,andfCLK=5.0MHzunlessotherwisespecified.BoldfacelimitsapplyforTA=TJ=TMINtoTMAX;allotherlimitsTA=TJ=25˚C.(Notes8,9,12)Symbol

Parameter

Conditions

Typical(Note10)

CINandCIWM

SuffixesLimits(Note11)

UNIPOLARCONVERTERANDMULTIPLEXERSTATICCHARACTERISTICS

ResolutionUnipolarIntegralLinearityError

UnipolarFull-ScaleErrorUnipolarOffsetErrorUnipolarTotalUnadjustedError(Note13)UnipolarPowerSupplySensitivity

OffsetErrorFull-ScaleError

IntegralLinearityError

ResolutionBipolarIntegralLinearityError

BipolarFull-ScaleError

VREF+=5.0VVREF=5.0V

+Units(Limit)

10+Sign

VREF+=2.5VVREF+=5.0VVREF=2.5VVREF+=5.0VVREF+=2.5V

+BitsLSBLSB(Max)LSBLSB(Max)LSBLSB(Max)LSBLSB(Max)

±0.5

±1

±0.5

±1.5

±1

±2

±1.5

±2.5

VREF=5.0VVREF+=2.5VVREF+=5.0V

+V=+5V±10%VREF+=4.5V

+±0.25±0.25±0.25

±1±1

LSB(Max)LSB(Max)LSB

BIPOLARCONVERTERANDMULTIPLEXERSTATICCHARACTERISTICS

10+Sign

BitsLSB(Max)LSB(Max)

±1±1.25

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ADC10154/ADC10158ElectricalCharacteristics

(Continued)

Parameter

Conditions

Typical(Note10)

CINandCIWM

SuffixesLimits(Note11)

BIPOLARCONVERTERANDMULTIPLEXERSTATICCHARACTERISTICS

BipolarNegativeFull-ScaleVREF+=5.0V

ErrorwithPositive-FullScaleAdjustedBipolarOffsetErrorBipolarTotalUnadjustedError(Note13)BipolarPowerSupplySensitivity

OffsetErrorFull-ScaleErrorIntegralLinearityError

MissingCodesDCCommonModeError(Note14)

BipolarUnipolar

RREFCREFVAICAIReferenceInputResistanceReferenceInputCapacitanceAnalogInputVoltageAnalogInputCapacitanceOffChannelLeakageCurrent(Note15)

OnChannel=5V

OffChannel=0VOnChannel=0VOffChannel=5V

30−400400

−10001000

VIN=

=VINwhere

+Units(Limit)

±1.25

VREF+=5.0VVREF+=5.0V

LSB(Max)LSB(Max)LSB(Max)

±2.5±3

V+=+5V±10%VREF+=4.5VV=−5V±10%VREF+=4.5V

−±0.5±0.5±0.25±0.25±0.25±0.25

±2.5±1.5±0.75±0.75

LSB(Max)LSB(Max)LSBLSB(Max)LSB(Max)LSB

UNIPOLARANDBIPOLARCONVERTERANDMULTIPLEXERSTATICCHARACTERISTICS

VIN−+5.0V≥VIN≥−5.0V+5.0V≥VIN≥0V±0.25±0.25

770

±0.75±0.5

4.59.5(V+0.05)(V−0.05)

−+LSB(Max)LSB(Max)kΩ(Max)kΩ(Max)pFV(Max)V(Min)pFnA(Max)nA(Max)

ElectricalCharacteristics

ThefollowingspecificationsapplyforV+=AV+=DV+=+5.0VDC,VREF+=5.000VDC,VREF−=GND,V−=GNDforunipolaroperationorV−=−5.0VDCforbipolaroperation,andfCLK=5.0MHzunlessotherwisespecified.BoldfacelimitsapplyforTA=TJ=TMINtoTMAX;allotherlimitsTA=TJ=25˚C.(Notes8,9,12)Symbol

Parameter

Conditions

Typical(Note10)

DYNAMICCONVERTERANDMULTIPLEXERCHARACTERISTICSS/(N+D)UnipolarSignal-to-Noise+fIN=10kHz,VIN=4.85Vp–pDistortionRatiofIN=150kHz,VIN=4.85Vp-pS/(N+D)

BipolarSignal-to-Noise+DistortionRatio

fIN=10kHz,VIN=±4.85V

fIN=150kHz,VIN=±4.85V

60586058

Limits(Note11)

Units(Limit)

dBdBdBdB

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ADC10154/ADC10158ElectricalCharacteristics

(Continued)

Parameter

Conditions

Typical(Note10)

DYNAMICCONVERTERANDMULTIPLEXERCHARACTERISTICS

−3dBUnipolarFullVIN=4.85Vp–pPowerBandwidth−3dBBipolarFullPowerBandwidth

REFERENCECHARACTERISTICS(UnipolarOperationV−=GNDOnly)VREFOut∆VREF/∆t∆VREF/∆ILReferenceOutputVoltageVREFOutTemperatureCoefficientLoadRegulationLineRegulation

ISC∆VREF/∆ttSUVIN(1)VIN(0)IIN(1)IIN(0)VOUT(1)ShortCircuitCurrentLong-TermStabilityStart-UpTime

Logical“1”InputVoltageLogical“0”InputVoltageLogical“1”InputCurrentLogical“0”InputCurrentLogical“1”OutputVoltage

CL=330µFV+=5.5V

V+=4.5VVIN=5.0VVIN=0VV+=4.5V:

IOUT=−360µAIOUT=−10µA

VOUT(0)IOUT+ISC−ISCDI+AII

−+Limits(Note11)Units(Limit)

200200

kHzkHz

VIN=±4.85V

2.5±1%40

0mA≤IL≤+4mA0mA≥IL≥−1mA4.5V≤V+≤5.5VVREFOut=0V

0.0030.20.51420020

2.5±2%0.10.6625

V(Max)ppm/˚C%/mA(Max)%/mA(Max)mV(Max)mA(Max)ppm/1kHr

SourcingSinking

DIGITALANDDCCHARACTERISTICS

2.00.8

0.005−0.005

2.5−2.52.44.250.4

−0.010.01−40300.750.15333.53.50.7

1.14.54.5−33−10102

V(Min)V(Max)µA(Max)µA(Max)V(Min)V(Min)V(Max)µA(Max)µA(Max)mA(Min)mA(Min)mA(Max)mA(Max)mA(Max)mA(Max)mA(Max)mA(Max)mA(Max)

Logical“0”OutputVoltageTRI-STATE®OutputCurrentOutputShortCircuitSourceCurrentOutputShortCircuitSinkCurrent

DigitalSupplyCurrentAnalogSupplyCurrentNegativeSupplyCurrentReferenceInputCurrent

V=4.5VIOUT=1.6mAVOUT=0V

+VOUT=5VVOUT=0VVOUT=DV+CS=HIGH

CS=HIGH,fCLK=0HzCS=HIGH

CS=HIGH,fCLK=0HzVREF+=5V

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ADC10154/ADC10158ElectricalCharacteristics

ACCHARACTERISTICSfCLKClockFrequencyClockDutyCycle

tCConversionTime

8-BitBipolarMode

fCLK=5.0MHz

10-BitUnipolarMode

fCLK=5.0MHz

10-BitBipolarMode

fCLK=5.0MHz

tAtCRtRCtCWtWCtRWtW(WR)tWStDStDHtWRtACCtWI,tRItINTLt1H,t0HtRRtPAcquisitionTime

fCLK=5.0MHz

DelaybetweenFallingEdgeofCSandFallingEdgeofRDDelaybetweeRisingEdgeRDandRisingEdgeofCSDelaybetweenFallingEdgeofCSandFallingEdgeofWRDelaybetweenRisingEdgeofWRandRisingEdgeofCSDelaybetweenFallingEdgeofRDandFallingEdgeofWRWRPulseWidth

WRHightoCLK÷2LowSet-UpTimeDataSet-UpTimeDataHoldTimeDelayfromRisingEdgeofWRtoRisingEdgeRDAccessTime(DelayfromFallingEdgeofRDtoOutputDataValid)DelayfromFallingEdgeofWRorRDtoResetofINTDelayfromFallingEdgeofCLK÷2toFallingEdgeofINT

TRI-STATEControl(DelayfromRisingEdgeofRDtoHi-ZState)DelaybetweenSuccessiveRDPulses

DelaybetweenLastRisingEdgeofRDandtheNextFallingEdgeofWRCINCOUTCapacitanceofLogicInputsCapacitanceofLogicOutputs

pFpF

ns(Min)

CL=10pF,RL=1kΩ

4020

nsns(Max)

CL=100pF

ns(Max)

CL=100pF

ns(Max)

60025

5051555

ns(Min)ns(Max)ns(Max)ns(Max)ns(Min)

ns(Min)

8-BitUnipolarMode

fCLK=5.0MHz

810

2080163.2183.6204.0224.461.255.0

MHz(Max)kHz(Min)%(Min)%(Max)1/fCLKµs(Max)1/fCLKµs(Max)1/fCLKµs(Max)1/fCLKµs(Max)1/fCLKµsns(Min)

Parameter

Conditions

Typical(Note10)

Limits(Note11)

Units(Limit)

Note1:AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.

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ADC10154/ADC10158ElectricalCharacteristics

(Continued)

Note2:OperatingRatingsindicateconditionsforwhichthedeviceisfunctional,butdonotguaranteespecificperformancelimits.Forguaranteedspecificationsandtestconditions,seetheElectricalCharacteristics.Theguaranteedspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmayde-gradewhenthedeviceisnotoperatedunderthelistedtestconditions.

Note3:AllvoltagesaremeasuredwithrespecttoGND,unlessotherwisespecified.

Note4:Whentheinputvoltage(VIN)atanypinexceedsthepowersupplies(VINAV+orDV+),thecurrentatthatpinshouldbelimitedto5mA.The20mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansafelyexceedthepowersupplieswithaninputcurrentof5mAtofour.

Note5:ThemaximumpowerdissipationmustbederatedatelevatedtemperaturesandisdictatedbyTJmax,θJAandtheambienttemperature,TA.ThemaximumallowablepowerdissipationatanytemperatureisPD=(TJmax−TA)/θJAorthenumbergivenintheAbsoluteMaximumRatings,whicheverislower.Forthisdevice,TJmax=150˚C.Thetypicalthermalresistance(θJA)ofthesepartswhenboardmountedfollow:ADC10154withBINandCINsuffixes65˚C/W,ADC10154withBIJ,CIJandCMJsuffixes49˚C/W,ADC10154withBIWMandCIWMsuffixes72˚C/W,ADC10158withBINandCINsuffixes59˚C/W,ADC10158withBIJ,CIJ,andCMJsuffixes46˚C/W,ADC10158withBIWMandCIWMsuffixes68˚C/W.

Note6:Humanbodymodel,100pFcapacitordischargedthrougha1.5kΩresistor.

Note7:SeeAN-450“SurfaceMountingMethodsandTheirEffectonProductReliability”orthesectiontitled“SurfaceMount”foundinanypost-1986NationalSemi-conductorLinearDataBookforothermethodsofsolderingsurfacemountdevices.

Note8:Twoon-chipdiodesaretiedtoeachanaloginputasshownbelow.Theywillforward-conductforanaloginputvoltagesonediodedropbelowV−supplyoronediodedropgreaterthanV+supply.BecarefulduringtestingatlowV+levels(4.5V),ashighlevelanaloginputs(5V)cancauseaninputdiodetoconduct,es-peciallyatelevatedtemperatures,whichwillcauseerrorsforanaloginputsnearfull-scale.Thespecificationallows50mVforwardbiasofeitherdiode;thismeansthataslongastheanalogVINdoesnotexceedthesupplyvoltagebymorethan50mV,theoutputcodewillbecorrect.Exceedingthisrangeonanunselectedchan-nelwillcorruptthereadingofaselectedchannel.ThismeansthatifAV+andDV+areminimum(4.5VDC)andV−isamaximum(−4.5VDC)fullscalemustbe≤±4.55VDC.

DS011225-4

Note9:AdiodeexistsbetweenAV+andDV+asshownbelow.

DS011225-5

Toguaranteeaccuracy,itisrequiredthattheAV+andDV+beconnectedtogethertoapowersupplywithseparatebypassfilterateachV+pin.Note10:TypicalsareatTJ=TA=25˚Candrepresentmostlikelyparametricnorm.

Note11:TestedlimitsareguaranteedtoNational’sAOQL(AverageOutgoingQualityLevel).Note12:OneLSBisreferencedto10bitsofresolution.

Note13:Totalunadjustederrorincludesoffset,full-scale,linearity,multiplexer,andholdsteperrors.Note14:ForDCCommonModeErrortheonlyspecificationthatismeasuredisoffseterror.Note15:Channelleakagecurrentismeasuredafterthechannelselection.

Note16:AllthetimingspecificationsaretestedattheTTLlogiclevels,VIL=0.8VforafallingedgeandVIH=2.0Vforarising.

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ADC10154/ADC10158ElectricalCharacteristics

(Continued)

DS011225-6

FIGURE1.TransferCharacteristic

DS011225-7

FIGURE2.SimplifiedErrorCurvevsOutputCode

OrderingInformation

Industrial−40˚C≤TA≤85˚CADC10154CIWMADC10158CINADC10158CIWM

PackageM24BN28BM28B

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ADC10154/ADC10158TypicalConverterPerformanceCharacteristics

TotalPositiveSupplyCurrent(DI++AI+)vsTemperature

TotalPositivePower

SupplyCurrent(DI++AI+)vsClockFrequency

OffsetErrorvsTemperature

DS011225-27

DS011225-28

DS011225-29

OffsetErrorvsReferenceVoltage

LinearityErrorvsTemperature

LinearityErrorvsReferenceVoltage

DS011225-30

DS011225-31

DS011225-32

LinearityErrorvsClockFrequency

SpectralResponsewith50kHzSineWave

10-BitUnsigned

Signal-to-Noise+THDRatiovsInputSignalLevel

DS011225-33DS011225-34

DS011225-35

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ADC10154/ADC10158TypicalReferencePerformanceCharacteristics

LoadRegulation

LineRegulation(3TypicalParts)

OutputDriftvsTemperature(3TypicalParts)

DS011225-36

DS011225-37

DS011225-38

Available

OutputCurrentvsSupplyVoltage

DS011225-39

LeakageCurrentTestCircuit

DS011225-10

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ADC10154/ADC10158TRI-STATETestCircuitsandWaveforms

DS011225-12

DS011225-11

DS011225-14

DS011225-13

TimingDiagrams

DS011225-15

DIAGRAM1.StartingaConversionwithNewMUXChannelandOutputConfiguration

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ADC10154/ADC10158TimingDiagrams

(Continued)

DS011225-16

DIAGRAM2.StartingaConversionwithoutChangingtheMUXChannelorOutputConfiguration

DS011225-17

DIAGRAM3.ReadingtheConversionResult

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ADC10154/ADC10158MultiplexerAddressingandOutputDataConfigurationTables

TABLE1.ADC10154andADC10158OutputDataConfiguration

OutputDataFormatRight-JustifiedLeft-JustifiedRight-JustifiedLeft-JustifiedRight-JustifiedLeft-JustifiedRight-JustifiedLeft-Justified

ControlInput

Data8/10U/SL/R

10-Bits+Sign10-Bits+Sign10-Bits10-Bits8-Bits+Sign8-Bits+Sign8-Bits8-Bits

LLLLHHHH

LLHHLLHH

LHLHLHLH

DB7Sign83L8MSB2SignMSBLSBLMSBMSBL

DB6Sign72L79LSBSign7LL77L

DB5Sign69LSBL68LSign67LL66L

DB4Sign58LL57LSign56LL55L

DB3Sign47LL46LSign45LL44L

DB236LL35LSign34LL33L

DB125LMSB24LSign23LL22L

DB09LSB4L9LSB3LSignLSB2LLLSBLSBL

FirstByteReadSecondByteReadFirstByteReadSecondByteReadFirstByteReadSecondByteReadFirstByteReadSecondByteReadFirstByteReadSecondByteReadFirstByteReadSecondByteReadFirstByteReadSecondByteReadFirstByteReadSecondByteRead

SignMSB

DataBusOutputAssignment

Resolution

SignMSB

TABLE2.ADC10158MultiplexerAddressing

MUXAddress

MA4MA3MA2MA1MA0XXXXXXXXLLLLLLLLHHHHHHHX

LLLLLLLLHHHHHHHHHHHHHHHX

LLLLHHHHLLLLHHHHLLLLHHHX

LLHHLLHHLLHHLLHHLLHHLLHX

LHLHLHLHLHLHLHLHLHLHLHLX

LLLLLLLLLLLLLLLLLLLLLLLL

LLLL

CSWRRDHHHHHHHHHHHHHHHHHHHHHHHL

+−

−+

+−

ChannelNumber

CH0CH1CH2CH3CH4CH5CH6CH7

VREF−MUXMode

−+

+−

−+

+−

−+

−−−

+−−−

−−−−

Pseudo-Differential

−−−−−

Single-EndedDifferential

PreviousChannelConfiguration

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ADC10154/ADC10158MultiplexerAddressingandOutputDataConfigurationTables

TABLE3.ADC10154MultiplexerAddressing

MUXAddress

MA4XXXXXXXXXXXX

MA3XXXXLLLLHHHX

MA2LLLLHHHHHHHX

MA1LLHHLLHHLLHX

MA0LHLHLHLHLHLX

LLLLLLLLLLLL

LLLL

(Continued)

CSWRRDCH0HHHHHHHHHHHL

+++−

ChannelNumberCH1−+

+−

−−−+

−−−−

CH2

CH3

VREF−MUXModeDifferential

Single-Ended

Pseudo-Differential

PreviousChannelConfiguration

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ADC10154/ADC10158DetailedBlockDiagram

DS011225-1815www.national.com

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ADC10154/ADC101581.0FunctionalDescription

TheADC10154andADC10158usesuccessiveapproxima-tiontodigitizeananaloginputvoltage.Additionallogichasbeenincorporatedinthedevicestoallowfortheprogramma-bilityoftheresolution,conversiontimeanddigitaloutputfor-mat.AcapacitivearrayandaresistiveladderstructureareusedintheDACportionoftheA/Dconverters.ThestructureoftheDACallowsaverysimpleswitchingschemetoprovideaveryversatileanaloginputmultiplexer.Also,inherentinthisstructureisasample/hold.A2.5VCMOSband-gapref-erenceisalsoprovidedontheADC10154andADC10158.1.1DIGITALINTERFACE

TheADC10154andADC10158haveeightdigitaloutputs(DB0–DB8)andcanbeeasilyinterfacedtoan8-bitdatabus.TakingCSandWRlowsimultaneouslywillstrobethedatawordonthedata-busintotheinputlatch.Thiswordwillbedecodedtodeterminethemultiplexerchannelselection,theA/Dconversionresolutionandtheoutputdataformat.Thefollowingtableshowstheinputworddata-bitassign-ment.

atelyaftertheacquisitionperiodtheinputsignalisheldandtheactualconversionbegins.Thenumberofclocksrequiredforaconversionisgiveninthefollowingtable:ConversionType8-Bit8-Bit+Sign10-Bit10-Bit+Sign

CLK÷2Cycles

891011

CLKCycles(N)

16182022

DS011225-44

DB0throughDB4areassignedtothemultiplexeraddressdatabitszerothroughfour(MA0–MA4).Tables2,3describethemultiplexeraddressassignment.DB5selectsunsignedorsigned(U/S)operation.DB6selects8-or10-bitresolu-tion.DB7selectsleftorrightjustificationoftheoutputdata.RefertoTable1fortheeffecttheControlInputDatahasonthedigitaloutputword.

TheconversionprocessisstartedbytherisingedgeofWR,whichsetsthe“startconversion”bitinsidetheADC.Ifthisbitisset,theconverterwillstartacquiringtheinputvoltageonthenextfallingedgeoftheinternalCLK÷2signal.Theacqui-sitionperiodis3CLK÷2periods,or6CLKperiods.Immedi-

SincetheCLK÷2signalisinternaltotheADC,itisinitiallyimpossibletoknowwhichfallingedgeofCLKcorrespondstothefallingedgeofCLK÷2.Forthefirstconversion,therisingedgeofWRshouldoccuratleasttWSnsbeforeanyfallingedgeofCLK.IfthisedgehappenstobeontherisingedgeofCLK÷2,thiswilladd2CLKcyclestothetotalconversiontime.ThephaseoftheCLK÷2signalcanbedeterminedattheendofthefirstconversion,whenINTgoeslow.INTal-waysgoeslowonthefallingedgeoftheCLK÷2signal.FromthefirstfallingedgeofINTonward,everyotherfallingedgeofCLKwillcorrespondtothefallingedgeofCLK÷2.WiththephaseofCLK÷2nowknown,theconversiontimecanbeminimizedbytakingWRhighatleasttWSnsbeforethefall-ingedgeofCLK÷2.

Uponcompletionoftheconversion,INTgoeslowtosignaltheA/Dconversionresultisreadytoberead.TakingCSandRDlowwillenablethedigitaloutputbufferandputbyte1oftheconversionresultonDB0throughDB7.ThefallingedgeofRDresetstheINToutputhigh.TakingCSandRDlowasecondtimewillputbyte2oftheconversionresultonDB7–DB0.Table1definestheDB0–DB7assignmentfordif-ferentControlInputData.Thesecondreaddoesnothavetobecompletedbeforeanewconversionisstarted.

TakingCS,WRandRDlowsimultaneouslywillstartacon-versionwithoutchangingthemultiplexerchannelassign-mentoroutputconfigurationandresolution.Thetimingdia-graminFigure3showsthesequenceofeventsthatimplementthisfunction.RefertoDiagrams1,2,and3intheTimingDiagramssectionforthetimingconstraintsthatmustbemet.

DS011225-19

FIGURE3.StartingaConversionwithoutUpdatingtheChannelConfiguration,Resolution,orDataFormat

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ADC10154/ADC101581.0FunctionalDescription

DigitalInterfaceHints:

(Continued)

••

ReadsandwritescanbecompletelyasynchronoustoCLK.

thedigitaloutput.ThisinformationisthenmanipulatedbytheDigitalOutputdecodertotheprogrammedformat.Therefor-matteddataisthenavailabletobestrobedontothedatabus(DB0–DB7)viathedigitaloutputbuffersbytakingCSandRDlow.

InadditiontothetimingindicatedinDiagrams1–3,CScanbetiedlowpermanentlyortakenlowforentirecon-versions,eliminatingalltheCSguardbands(tCR,tRC,tCW,tWC).

•IfCSisusedasshowninDiagrams1–-3,theCSguard-bands(tCR,tRC,tCW,tWC)betweenCSandtheRDandWRsignalscansafelybeignoredaslongasthefollow-ingtwoconditionsaremet:

1)Wheninitiatingawrite,CSandWRmustbesimulta-neouslylowforatleasttW(WR)ns(seeDiagram1).The“start”conversion”bitwillbesetontherisingedgeofWRorCS,whicheverisfirst.

2)Whenreadingdata,understandthatdatawillnotbevalid

untiltACCnsafterbothCSandRDgolow.TheoutputdatawillenterTRI-STATEt1Hnsort0HnsaftereitherCSorRDgoeshigh(seeDiagrams2and3).1.2ARCHITECTURE

Beforeaconversionisstarted,duringtheanaloginputsam-plingperiod,thesampleddatacomparatoriszeroed.AsthecomparatorisbeingzeroedthechannelassignedtobethepositiveinputisconnectedtotheA/D’sinputcapacitor.(SeetheDigitalInterfacesectionforadescriptionoftheassign-mentprocedure.)Thischargestheinput32CcapacitoroftheDACtothepositiveanaloginputvoltage.TheswitchesshownintheDACportionofthedetailedblockdiagramaresetforthiszeroing/acquisitionperiod.Thevoltageatthein-putandoutputofthecomparatorareatequilibriumatthispointintime.Whentheconversionisstartedthecomparatorfeedbackswitchesareopenedandthe32Cinputcapacitoristhenswitchedtotheassignednegativeinputvoltage.Whenthecomparatorfeedbackswitchopensafixedamountofchargeistrappedonthecommonplatesofthecapacitors.Thevoltageattheinputofthecomparatormovesawayfromequilibriumwhenthe32Ccapacitorisswitchedtotheas-signednegativeinputvoltage,causingtheoutputofthecom-paratortogohigh(“1”)orlow(“0”).TheSARnextgoesthroughanalgorithm,controlledbytheoutputstateofthecomparator,thatredistributesthechargeonthecapacitorar-raybyswitchingthevoltageononesideofthecapacitorsinthearray.TheobjectiveoftheSARalgorithmistoreturnthevoltageattheinputofthecomparatorascloseaspossibletoequilibrium.

Theswitchpositioninformationatthecompletionofthesuc-cessiveapproximationroutineisadirectrepresentationof

2.0ApplicationsInformation

2.1MULTIPLEXERCONFIGURATION

Thedesignoftheseconvertersutilizesasampled-datacom-paratorstructurewhichallowsadifferentialanaloginputtobeconvertedbythesuccessiveapproximationroutine.

Theactualvoltageconvertedisalwaysthedifferencebe-tweenanassigned“+”inputterminalanda“−”inputterminal.Thepolarityofeachinputterminalorpairofinputterminalsbeingconvertedindicateswhichlinetheconverterexpectstobethemostpositive.Iftheassigned“+”inputislessthanthe“−”inputtheconverterrespondswithanallzerosoutputcodewhenconfiguredforunsignedoperation.Whenconfig-uredforsignedoperationtheA/Drespondswiththeappro-priateoutputdigitalcode.

Auniqueinputmultiplexingschemehasbeenutilizedtopro-videmultipleanalogchannels.Theinputchannelscanbesoftwareconfiguredintothreemodes:differential,single-ended,orpseudo-differential.Figure4showsthethreemodesusingthe4-channelMUXoftheADC10154.TheeightinputsoftheADC10158canalsobeconfiguredinanyofthethreemodes.Thesingle-endedmodehasCH0–CH3assignedasthepositiveinputwiththenegativeinputbeingtheVREF−ofthedevice.Inthedifferentialmode,theADC10154channelinputsaregroupedinpairs,CH0withCH1andCH2withCH3.Thepolarityassignmentofeachchannelinthepairisinterchangeable.Finally,inthepseudo-differentialmodeCH0–CH2arepositiveinputsre-ferredtoCH3whichisnowapseudo-ground.Thispseudo-groundinputcanbesettoanypotentialwithinthein-putcommon-moderangeoftheconverter.Theanalogsignalconditioningrequiredintransducer-baseddataacquisitionsystemsissignificantlysimplifiedwiththistypeofinputflex-ibility.Oneconverterpackagecannowhandleground-referredinputsandtruedifferentialinputsaswellassignalsreferredtoaspecificvoltage.

Theanaloginputvoltagesforeachchannelcanrangefrom50mVbelowV−(typicallygroundforunipolaroperationor−5Vforbipolaroperation)to50mVaboveV+=DV+=AV+(typically5V)withoutdegradingconversionaccuracy.Ifthevoltageonanunselectedchannelexceedstheselimitsitmaycorruptthereadingoftheselectedchannel.

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2.0ApplicationsInformation

(Continued)

2.2REFERENCECONSIDERATIONS

ThevoltagedifferencebetweentheVREF+andVREF−inputsdefinestheanaloginputvoltagespan(thedifferencebe-tweenVIN(Max)andVIN(Min))overwhichthe2n(wherenistheprogrammedresolution)possibleoutputcodesapply.Inthepseudo-differentialanddifferentialmodestheactualvolt-ageappliedtoVREF+andVREF−canlieanywherebetweentheAV+andV−.Onlythedifferencevoltageisofimportance.Whenusingthesingle-endedmultiplexermodethevoltageatVREF−hasadualfunction.Itsimultaneouslydeterminesthe“zero”referencevoltageand,withVREF+,theanalogvolt-agespan.

ThevalueofthevoltageontheVREF+orVREF−inputscanbeanywherebetweenAV++50mVandV−−50mV,solongasVREF+isgreaterthanVREF−.TheADC10154andADC10158canbeusedineitherratiometricapplicationsorinsystemsrequiringabsoluteaccuracy.Thereferencepinsmustbeconnectedtoavoltagesourcecapableofdrivingthemini-mumreferenceinputresistanceof4.5kΩ.

Theinternal2.5VbandgapreferenceintheADC10154andADC10158isavailableasanoutputontheVREFOutpin.Toensureoptimumperformancethisoutputneedstobeby-passedtogroundwith330µFaluminumelectrolyticortanta-lumcapacitor.Thereferenceoutputisunstablewithcapaci-tiveloadsgreaterthan100pFandlessthan100µF.Anycapacitiveloads≤100pFor≥100µFwillnotcausetherefer-encetooscillate.Loweroutputnoisecanbeobtainedbyin-creasingtheoutputcapacitance.The330µFcapacitorwillyieldatypicalnoisefloorof200nVrms/

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ADC10154/ADC101582.0ApplicationsInformation

(Continued)

DS011225-21

a.RatiometricUsingtheInternalReference

DS011225-22

b.AbsoluteUsinga4.096VSpan

FIGURE5.DifferentReferenceConfigurations

TheminimumvalueofVREF(VREF=VREF+−VREF−)canbequitesmall(seeTypicalPerformanceCharacteristics)toal-lowdirectconversionoftransduceroutputsprovidinglessthana5Voutputspan.Particularcaremustbetakenwithre-gardtonoisepickup,circuitlayoutandsystemerrorvoltagesourceswhenoperatingwithareducedspanduetothein-creasedsensitivityoftheconverter(1LSBequalsVREF/2n).2.3THEANALOGINPUTS

Duetothesamplingnatureoftheanaloginputs,attheclockedgesshortdurationspikesofcurrentwillbeseenonthese-lectedassignednegativeinput.Inputbypasscapacitorsshouldnotbeusedifthesourceresistanceisgreaterthan1kΩsincetheywillaveragetheACcurrentandcauseanef-fectiveDCcurrenttoflowthroughtheanaloginputsourcere-sistance.AnopampRCactivelowpassfiltercanprovidebothimpedancebufferingandnoisefilteringshouldahighimpedancesignalsourceberequired.Bypasscapacitorsmaybeusedwhenthesourceimpedanceisverylowwithoutanydegradationinperformance.

Inatruedifferentialinputstage,asignalthatiscommontoboth“+”and“−”inputsiscancelled.FortheADC10154andADC10158,thepositiveinputofaselectedchannelpairisonlysampledoncebeforethestartofaconversionduring

theacquisitiontime(tA).ThenegativeinputneedstobestableduringthecompleteconversionsequencebecauseitissampledbeforeeachdecisionintheSARsequence.Therefore,anyACcommon-modesignalpresentontheana-loginputswillnotbecompletelycancelledandwillcausesomeconversionerrors.Forasinusoidcommon-modesig-nalthiserroris:

Verror(Max)=VPEAK(2πfCM)(tC)

wherefCMisthefrequencyofthecommon-modesignal,VPEAKisitspeakvoltagevalue,andtCistheA/D’smaximumconversiontime(tC=22/fCLKfor10-bitplussignresolution).Forexample,fora60Hzcommon-modesignaltogeneratea1⁄4LSBerror(1.24mV)witha4.5µsconversiontime,itspeakvaluewouldhavetobeapproximately731mV.2.4OPTIONALADJUSTMENTS2.4.1ZeroError

ThezeroerroroftheA/Dconverterrelatestothelocationofthefirstriserofthetransferfunction(seeFigure1)andcanbemeasuredbygroundingtheminusinputandapplyingasmallmagnitudepositiveornegativevoltagetotheplusin-put.ZeroerroristhedifferencebetweenactualDCinputvoltagewhichisnecessarytojustcauseanoutputdigital

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ADC10154/ADC101582.0ApplicationsInformation

(Continued)

codetransitionfrom00000000000to00000000001(10-bitsplussign)andtheideal1⁄2LSBvalue(1⁄2LSB=2.44mVforVREF=+5.000Vand10-bitplussignresolution).ThezeroerroroftheA/Ddoesnotrequireadjustment.Iftheminimumanaloginputvoltagevalue,VIN(Min),isnotground,theeffetive“zero”voltagecanbeadjustedtoaconvenientvalue.Theconvertercanbemadetooutputanallzerosdigi-talcodeforthisminimuminputvoltagebybiasinganyminusinputtoVIN(Min).Thisisusefulforeitherthedifferentialorpseudo-differentialinputchannelconfigurations.

2.4.2Full-Scale

Thefull-scaleadjustmentcanbemadebyapplyingadiffer-entialinputvoltagewhichis11⁄2LSBdownfromthedesiredanalogfull-scalevoltagerangeandthenadjustingtheVREFvoltage(VREF=VREF+−VREF−)foradigitaloutputcodechangingfrom01111111110to01111111111.Inbipolarsignedoperationthisonlyadjuststhepositivefullscaleerror.Thenegativefull-scaleerrorwillbeasspecifiedintheElec-tricalCharacteristicsafterapositivefull-scaleadjustment.2.4.3AdjustingforanArbitraryAnalogInputVoltageRange

IftheanalogzerovoltageoftheA/Disshiftedawayfromground(forexample,toaccommodateananaloginputsignalwhichdoesnotgotoground),thisnewzeroreferenceshouldbeproperlyadjustedfirst.Aplusinputvoltagewhichequalsthisdesiredzeroreferenceplus1⁄2LSB(wheretheLSBiscalculatedforthedesiredanalogspan,using1LSB=analogspan/2n,nbeingtheprogrammedresolution)isap-pliedtoselectedplusinputandthezeroreferencevoltageatthecorrespondingminusinputshouldthenbeadjustedtojustobtainthe000HEXto001HEXcodetransition.

Thefull-scaleadjustmentshouldbemade[withtheproperminusinputvoltageapplied]byforcingavoltagetotheplusinputwhichisgivenby:

analoginputvoltage.AnychangeintheanalogvoltageonaselectedpositiveinputbeforeoraftertheacquisitionwindowwillnoteffecttheA/Dconversionresult.

Inthesimplestcase,thearray’sacquisitiontimeisdeter-minedbytheRON(9kΩ)ofthemultiplexerswitches,thestrayinputcapacitanceCS1(3.5pF)andthetotalarray(CL)andstray(CS2)capacitance(CL+CS2=48pF).ForalargesourceresistancetheanaloginputcanbemodeledasanRCnetworkasshowninFigure6.Thevaluesshownyieldanacquisitiontimeofabout1.1µsfor10-bitunipolaror10-bitplussignbipolaraccuracywithazero-to-full-scalechangeintheinputvoltage.Externalsourceresistanceandcapaci-tancewilllengthentheacquisitiontimeandshouldbeac-countedfor.Slowingtheclockwilllengthentheacquisitiontime,therebyallowingalargerexternalsourceresistance.

DS011225-23

FIGURE6.AnalogInputModel

Thecurve“SignaltoNoiseRatiovs.OutputFrequency”(Fig-ure7)givesanindicationoftheusablebandwidthoftheADC10154/ADC10158.Thesignal-to-noiseratioofanidealA/DistheratiooftheRMSvalueofthefullscaleinputsignalamplitudetothevalueofthetotalerroramplitude(includingnoise)causedbythetransferfunctionoftheA/D.Anideal10-bitplussignA/Dconverterwithatotalunadjustederrorof0LSBwouldhaveasignal-to-noiseratioofabout68dB,whichcanbederivedfromtheequation:

S/N=6.02(n)+1.76

whereS/NisindBandnisthenumberofbits.Figure3showsthesignal-to-noiseratiovs.inputfrequencyofatypi-calADC10154/ADC10158with1⁄2LSBtotalunadjusteder-ror.Thedottedlinesshowsignal-to-noiseratiosforanideal(noiseless)10-bitA/Dwith0LSBerrorandanA/Dwitha1LSBerror.

SNRvsInputFrequency

whereVMAXequalsthehighendoftheananloginputrange,VMINequalsthelowend(theoffsetzero)oftheanalograngeandnequalstheprogrammedresolution.BothVMAXandVMINaregroundreferred.TheVREF(VREF=VREF+−VREF−)voltageisthenadjustedtoprovideacodechangefrom3FEHEXto3FFHEX.Note,whenusingapseudo-differentialordifferentialmultiplexermodewhereVREF+andVREF−areplacedwithintheV+andV−range,theindividualvaluesofVREF+andVREF−donotmatter,onlythedifferencesetstheanaloginputvoltagespan.Thiscompletestheadjustmentprocedure.

2.5INPUTSAMPLE-AND-HOLD

TheADC10154/8’ssample/holdcapacitorisimplementedinthecapacitorarray.Afterthechanneladdressisloaded,thearrayisswitchedtosampletheselectedpositiveanalogin-put.TherisingedgeofWRloadsthemultiplexeraddressinginformation.Thesamplingperiodfortheassignedpositiveinputismaintainedforthedurationoftheacquisitiontime(tA),i.e.,approximately6to8clockcyclesaftertherisingedgeofWR.Anacquisitionwindowof6clockcyclesisavailabletoallowthevoltageonthecapacitorarraytosettletothepositive

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DS011225-24

FIGURE7.ADC10154/ADC10158

Signal-to-NoiseRatiovsInputFrequency

Thesample-and-holderrorspecificationsareincludedintheerrorandtimingspecificationsoftheA/D.Theholdstepand

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ADC10154/ADC101582.0ApplicationsInformation

(Continued)

gainerrorsample/holdspecsareincludedintheADC10154/ADC10158’stotalunadjusted,linearity,gainandoffseterrorspecifications,whiletheholdsettlingtimeisincludedinthe

A/D’smaximumconversiontimespecification.Theholddroopratecanbethoughtofasbeingzerosinceanunlim-itedamountoftimecanpassbetweenaconversionandthereadingofdata.Thedataislostafteranewconversionhasbeencompleted.

ProtectingtheAnalogInputs

DS011225-25

Diodesare1N914.

Theprotectiondiodesshouldbeabletowithstandtheoutputcurrentoftheopampundercurrentlimit.

Zero-ShiftandSpan-AdjustforSignedorUnsigned,Unipolar,Single-Ended

MultiplexerAssignment,AnalogInputRangeof2V≤VIN≤4.5V

DS011225-26

*1%resistors

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ADC10154/ADC10158PhysicalDimensions

inches(millimeters)unlessotherwisenoted

Dual-In-LinePackage(M)OrderNumberADC10154CIWMNSPackageNumberM24B

Dual-In-LinePackage(M)OrderNumberADC10158CIWMNSPackageNumberM28B

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ReferencePhysicalDimensions

inches(millimeters)unlessotherwisenoted(Continued)

Dual-In-LinePackage(N)

OrderNumberADC10158BINorADC10158CIN

NSPackageNumberN28B

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labeling,canbereasonablyexpectedtoresultinasignificantinjurytotheuser.

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