M16C/30P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0088-0122
Rev.1.22Mar 30, 2007
1.Overview
The M16C/30P Group of single-chip microcomputers is built using the high-performance silicon gate CMOS processusing a M16C/60 Series CPU core and is packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instructionefficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. In addition, thesemicrocomputers contain a multiplier and DMAC which combined with fast instruction processing capability, make itsuitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.
1.1Applications
Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc.
Rev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
1. Overview
1.2Performance Outline
Performance Outline of M16C/30P Group
Table 1.1 lists Performance Outline of M16C/30P Group.Table 1.1
ItemPerformance
CPUNumber of Basic Instructions91 instructions
Minimum Instruction 62.5ns(f(XIN)=16MHz, VCC1=VCC2=3.0 to 5.5V, no wait)Execution Time100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait)Operation ModeSingle-chip, memory expansion and microprocessor
mode
Memory Space1 MbyteMemory CapacitySee Table 1.2 Product List
Peripheral PortInput/Output : 87 pins, Input : 1 pinFunction Multifunction TimerTimer A : 16 bits x 3 channels,
Timer B : 16 bits x 3 channels
Serial Interface1 channels
Clock synchronous, UART, I2CBus(1), IEBus(2)2 channels
Clock synchronous, UART, I2CBus(1)
A/D Converter 10-bit A/D converter: 1 circuit, 18 channelsDMAC2 channelsCRC Calculation CircuitCCITT-CRC Watchdog Timer15 bits x 1 channel (with prescaler)InterruptInternal: 20 sources, External: 7 sources, Software: 4
sources, Priority level: 7 levels
Clock Generating Circuit2 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
(*)Equipped with a built-in feedback resistor.
Electric Supply VoltageVCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz)CharacteristicsVCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait)
Power Consumption10 mA (VCC1=VCC2=5V, f(XIN)=16MHz)
8 mA (VCC1=VCC2=3V, f(XIN)=10MHz)
1.8 μA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)0.7 μA(VCC1=VCC2=3V, stop mode)
One time flash Program Supply Voltage3.3±0.3 V or 5.0±0.5 Vversion
Flash memory Program/Erase Supply 3.3±0.3 V or 5.0±0.5 VversionVoltage
Program and Erase 100 times (all area)Endurance
Operating Ambient Temperature-20 to 85°C, -40 to 85°CPackage100-pin plastic mold QFP, LQFPNOTES:
1.I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.2.IEBus is a registered trademark of NEC Electronics Corporation.3.Use the M16C/30P on VCC1 = VCC2.
Rev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
1. Overview
1.3Block Diagram
Figure 1.1 is a M16C/30P Group Block Diagram.
8888888Port P0Port P1Port P2Port P3Port P4Port P5Port P6Port P7Internal peripheral functions8 A/D converterTimer (16-bit)Output (timer A): 3Input (timer B): 3(10 bits X 18 channels)UART orclock synchronous serial I/OSystem clockgeneration circuitXIN-XOUTXCIN-XCOUTPort P87(3 channels)Port P8_5CRC arithmetic circuit (CCITT )(Polynomial : X16+X12+X5+1)M16C/60 series16-bit CPU coreWatchdog timer(15 bits)R0HR1HR2R3A0A1FBR0LR1LSBUSPISPINTBPCFLGMemoryROM (1)RAM (2)Port P98DMAC(2 channels)Port P10Multiplier8NOTES :1. ROM size depends on microcomputer type.2. RAM size depends on microcomputer type.Figure 1.1M16C/30P Group Block DiagramRev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
1. Overview
1.4Product List
Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Part No., Memory Size, and Package. Table1.4 lists Product Code of MASK ROM version for M16C/30P. Figure 1.3 shows the Marking Diagram of MaskROM Version for M16C/30P (Top View). Table 1.5 lists Product Code of One Time Flash version, Flash Memoryversion, and ROM-less version for M16C/30P. Figure 1.4 shows the Marking Diagram of One Time Flash version,Flash Memory version, and ROM-less Version for M16C/30P (Top View). Please specify the marking forM16C30P (MASK ROM version) when placing an order for ROM.Table 1.2
Product List (1)
ROM Capacity96 Kbytes128 Kbytes160 Kbytes192 Kbytes96 Kbytes(D)
128 Kbytes(D)
160 Kbytes(D)(D)(D)
192 Kbytes(D)(D)(D)(D)(D)(D)
128 Kbytes(D)
160 Kbytes(D)(D)(D)
192 Kbytes(D)(D)(D)(D)(D)
6 Kbytes12 Kbytes6 Kbytes12 Kbytes
256 Kbytes
12 Kbytes6 Kbytes12 Kbytes6 Kbytes12 Kbytes
256 Kbytes96 Kbytes
12 Kbytes5 Kbytes5 Kbytes6 KbytesRAM Capacity5 Kbytes
package code (1)PRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-A
As of March 2007RemarksMask ROM version
Part No.
M30302MAP-XXXFPM30302MAP-XXXGPM30302MCP-XXXFPM30302MCP-XXXGPM30302MDP-XXXFPM30302MDP-XXXGPM30302MEP-XXXFPM30302MEP-XXXGPM30302GAPFPM30302GAPGPM30302GCPFPM30302GCPGPM30302GDPFPM30302GDPGPM30304GDPFPM30304GDPGPM30302GEPFPM30302GEPGPM30304GEPFPM30304GEPGPM30302GGPFPM30302GGPGP
M30302GAP-XXXFPM30302GAPvGPM30302GCP-XXXFPM30302GCP-XXXGPM30302GDP-XXXFPM30302GDP-XXXGPM30304GDP-XXXFPM30304GDP-XXXGPM30302GEP-XXXFPM30302GEP-XXXGPM30304GEP-XXXFPM30304GEP-XXXGPM30302GGP-XXXFPM30302GGP-XXXGP
One Time Flashversion
(blank product)
One Time Flashversion
(factory programmed product)
(D): Under development(P): Under planningNOTES:
1.Previous package codes are as follows.
PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A
2.Block A (4-Kbytes space) is available in flash memory version.
Rev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
Table 1.3
Product List (2)
ROM Capacity96 K + 4 Kbytes128 K + 4 Kbytes192 K + 4 Kbytes-6 Kbytes6 KbytesRAM Capacity5 Kbytes
package code (1)PRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-APRQP0100JB-APLQP0100KB-A
1. Overview
As of March 2007RemarksFlash memory version(2)
Part No.
M30302FAPFPM30302FAPGPM30302FCPFPM30302FCPGPM30302FEPFPM30302FEPGPM30302SPFPM30302SPGP
ROM-less version
(D): Under development(P): Under planningNOTES:
1.Previous package codes are as follows.
PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A
2.Block A (4-Kbytes space) is available in flash memory version.
Part No.M 3 0 3 0 2 M E P - X X X H PPackage type:FP : Package PRQP0100JB-A (100P6S-A)GP : Package PLQP0100KB-A (100P6Q-A)ROM No.M16C/30P GroupROM capacity:A: 96 KbytesC:128 KbytesD:160 KbytesE:192 KbytesG:256 KbytesMemory type:M:Mask ROM versionG:One Time Flash versionF:Flash Memory versionS:ROM-less versionShows RAM capacity, pin count, etc(The value itself has no specific meaning)M16C/30 SeriesM16C FamilyFigure 1.2Part No., Memory Size, and PackageRev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
1. Overview
Table 1.4
Product Code
Product Code of MASK ROM version for M16C/30P
Package
Operating Ambient Temperature
-20°C to 85°C
U1 Lead-freeU4 -40°C to 85°C
PRQP0100JB-A (100P6S-A)1. Standard Renesas MarkM16CM30302MDP-XXXFPAU1XXXXXXXPart No. (See Figure 1.2 Part No., Memory Size, and Package)Chip version, product code and date codeA: Shows chip version. Henceforth, whenever it changes a version,it continues with A, B, and C.U1: Shows Product code. (See table 1.3 Product Code)XXXXXXX: Seven digits2. Customer’s Parts Number + Renesas catalog nameM30302MDP-XXXFPAU1M16CXXXXXXXPart No. (See Figure 1.2 Part No., Memory Size, and Package)Chip version and product codeA:Shows chip version.Henceforth, whenever it changes a version,it continues with A, B, and C.U1:Shows Product code. (See table 1.3 Product Code)Date code seven digitsPLQP0100KB-A (100P6Q-A)1. Standard Renesas MarkM16CM30302MDP-XXXGPAU1XXXXXXXPart No. (See Figure 1.2 Part No., Memory Size, and Package)Chip version, product code and date codeA:Shows chip version.Henceforth, whenever it changes a version,it continues with A, B, and C.U1:Shows Product code. (See table 1.3 Product Code)XXXXXXX:Seven digits2. Customer’s Parts Number + Renesas catalog nameM30302MDPAU1-XXXGPM16CXXXXXXXPart No. (See Figure 1.2 Part No., Memory Size, and Package)Chip version and product codeA:Shows chip version.Henceforth, whenever it changes a version,it continues with A, B, and C.U1:Shows Product code. (See table 1.3 Product Code)Date code seven digitsNOTES:1. Refer to the mark specification form for details of the Mask ROM version marking.Figure 1.3Marking Diagram of Mask ROM Version for M16C/30P (Top View)Page 6 of 53
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M16C/30P Group
1. Overview
Table 1.5
Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P
Internal ROM
Product Code
One Time Flash versionFlash Memory version
ROM-less version
Package
Programand EraseEndurance
TemperatureRange
Operating AmbientTemperature
0°C to 60°CU3 Lead-0-40°C to 85°C
freeU5 -20°C to 85°C0°C to 60°CU3 Lead-100-40°C to 85°CfreeU5 -20°C to 85°C−−Lead--40°C to 85°CfreeU5 -20°C to 85°C
U3
NOTES:The one time flash version can be written once only.
PRQP0100JB-A (100P6S-A)M1M30302SPAXXXXX6FUXCP3XPart No. (See Figure 1.2 Part No., Memory Size, and Package)Chip version and product codeA:Shows chip version.Henceforth, whenever it changes a version,it continues with A, B, and C.U3:Shows Product code. (See table 1.3 Product Code)Date code seven digitsPLQP0100KB-A (100P6Q-A)M16CM30302SPGPAU3XXXXXXXPart No. (See Figure 1.2 Part No., Memory Size, and Package)Chip version and product codeA:Shows chip version.Henceforth, whenever it changes a version,it continues with A, B, and C.U3:Shows Product code. (See table 1.3 Product Code)Date code seven digitsThe product without marking of chip version of One Time Flash version, FlashMemory version, and the ROMless version corresponds to the chip version “A”.Figure 1.4Marking Diagram of One Time Flash version, Flash Memory version, and ROM-less Version for M16C/30P (Top View)Rev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
1. Overview
1.5Pin Configuration
Figures 1.5 to 1.6 show the pin configurations (top view).
PIN CONFIGURATION (top view)P1_0/D8P1_1/D9P1_2/D10P1_3/D11P1_4/D12P1_5/D13/INT3P1_6/D14/INT4P1_7/D15P2_0/A0P2_1/A1P2_2/A2P2_3/A3P2_4/A4P2_5/A5P2_6/A6P2_7/A7VSSP3_0/A8VCC2P3_1/A9P3_2/A10P3_3/A11P3_4/A12P3_5/A13P3_6/A14P3_7/A15P4_0/A16P4_1/A17P4_2/A18P4_3/A1980797877767574737271706968676665636261605958575655535251P0_7/AN0_7/D7P0_6/AN0_6/D6P0_5/AN0_5/D5P0_4/AN0_4/D4P0_3/AN0_3/D3P0_2/AN0_2/D2P0_1/AN0_1/D1P0_0/AN0_0/D0P10_7/AN7/KI3P10_6/AN6/KI2P10_5/AN5/KI1P10_4/AN4/KI0P10_3/AN3P10_2/AN2P10_1/AN1AVSSP10_0/AN0VREFAVCCP9_7/ADTRG818283848586878091929394959697991001234567101112131415161718192021222324252627282930504948474443424140393837363534333231M16C/30P GroupP4_4/CS0P4_5/CS1P4_6/CS2P4_7/CS3P5_0/WRL/WRP5_1/WRH/BHEP5_2/RDP5_3/BCLKP5_4/HLDAP5_5/HOLDP5_6/ALEP5_7/RDY/CLKOUTP6_0/CTS0/RTS0P6_1/CLK0P6_2/RXD0/SCL0P6_3/TXD0/SDA0P6_4/CTS1/RTS1/CTS0/CLKS1P6_5/CLK1P6_6/RXD1/SCL1P6_7/TXD1/SDA1NOTES:1. P7_0 and P7_1 are N channel open-drain output pins.2. Use the M16C/30P on VCC1=VCC2.Figure 1.5Pin Configuration (Top View)Rev.1.22Mar 30, 2007REJ03B0088-0122
P9_6/ANEX1P9_5/ANEX0P9_4P9_3P9_2/TB2INP9_1/TB1INP9_0/TB0INBYTECNVSSP8_7/XCINP8_6/XCOUTRESETXOUTVSSXINVCC1P8_5/NMIP8_4/INT2P8_3/INT1P8_2/INT0P8_1P8_0P7_7P7_6P7_5/TA2INP7_4/TA2OUTP7_3/CTS2/RTS2/TA1INP7_2/CLK2/TA1OUTP7_1/RXD2/SCL2/TA0IN(1)P7_0/TXD2/SDA2/TA0OUT(1)Package : PRQP0100JB-A (100P6S-A)Page 8 of 53
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M16C/30P Group
1. Overview
PIN CONFIGURATION (top view)P1_3/D11P1_4/D12P1_5/D13/INT3P1_6/D14/INT4P1_7/D15P2_0/A0P2_1/A1P2_2/A2P2_3/A3P2_4/A4P2_5/A5P2_6/A6P2_7/A7VSSP3_0/A8VCC2P3_1/A9P3_2/A10P3_3/A11P3_4/A12P3_5/A13P3_6/A14P3_7/A15P4_0/A16P4_1/A177574737271706968676665636261605958575655535251P1_2/D10P1_1/D9P1_0/D8P0_7/AN0_7/D7P0_6/AN0_6/D6P0_5/AN0_5/D5P0_4/AN0_4/D4P0_3/AN0_3/D3P0_2/AN0_2/D2P0_1/AN0_1/D1P0_0/AN0_0/D0P10_7/AN7/KI3P10_6/AN6/KI2P10_5/AN5/KI1P10_4/AN4/KI0P10_3/AN3P10_2/AN2P10_1/AN1AVSSP10_0/AN0VREFAVCCP9_7/ADTRGP9_6/ANEX1P9_5/ANEX0767778798081828384858687809192939495969799100123456710111213141516171819202122232425504948474443424140M16C/30P Group3938373635343332313029282726P4_2/A18P4_3/A19P4_4/CS0P4_5/CS1P4_6/CS2P4_7/CS3P5_0/WRL/WRP5_1/WRH/BHEP5_2/RDP5_3/BCLKP5_4/HLDAP5_5/HOLDP5_6/ALEP5_7/CLKOUTP6_0/CTS0/RTS0P6_1/CLK0P6_2/RXD0/SCL0P6_3/TXD0/SDA0P6_4/CTS1/RTS1/CTS0/CLKS1P6_5/CLK1P6_6/RXD1/SCL1P6_7/TXD1/SDA1P7_0/TXD2/SDA2/TA0OUT(1)P7_1/RXD2/SCL2/TA0IN(1)P7_2/CLK2/TA1OUTNOTES:1. P7_0 and P7_1 are N channel open-drain output pins.2. Use the M16C/30P on VCC1=VCC2.Figure 1.6Pin Configuration (Top View)Rev.1.22Mar 30, 2007REJ03B0088-0122
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P9_4P9_3P9_2/TB2INP9_1/TB1INP9_0/TB0INBYTECNVSSP8_7/XCINP8_6/XCOUTRESETXOUTVSSXINVCC1P8_5/NMIP8_4/INT2P8_3/INT1P8_2/INT0P8_1P8_0P7_7P7_6P7_5/TA2INP7_4/TA2OUTP7_3/CTS2/RTS2/TA1INPackage : PLQP0100KB-A (100P6Q-A)元器件交易网www.cecb2b.com
M16C/30P Group
1. Overview
Table 1.6
Pin No.FPGP
1234567101112131415161718192021222324252627282930313233343536373839404142434447484950
99100123456710111213141516171819202122232425262728293031323334353637383940414243444748
Pin Characteristics (1)
Control Pin
Port
P9_6P9_5P9_4P9_3P9_2P9_1P9_0
BYTECNVSSXCINXCOUTRESETXOUTVSSXINVCC1
P8_5P8_4P8_3P8_2P8_1P8_0P7_7P7_6P7_5P7_4P7_3P7_2P7_1P7_0P6_7P6_6P6_5P6_4P6_3P6_2P6_1P6_0P5_7P5_6P5_5P5_4P5_3P5_2P5_1P5_0P4_7P4_6P4_5P4_4
TA2INTA2OUTTA1INTA1OUTTA0INTA0OUT
CTS2/RTS2CLK2RXD2/SCL2TXD2/SDA2TXD1/SDA1RXD1/SCL1CLK1
CTS1/RTS1/CTS0/CLKS1TXD0/SDA0RXD0/SCL0CLK0CTS0/RTS0
RDY/CLKOUTALEHOLDHLDABCLKRDWRH/BHEWRL/WRCS3CS2CS1CS0
NMIINT2INT1INT0
P8_7P8_6
TB2INTB1INTB0IN
Interrupt PinTimer PinUART PinAnalog Pin
ANEX1ANEX0
Bus Control
Pin
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M16C/30P Group
1. Overview
Table 1.7Pin Characteristics (2)
Port
P4_3P4_2P4_1P4_0P3_7P3_6P3_5P3_4P3_3P3_2P3_1P3_0P2_7P2_6P2_5P2_4P2_3P2_2P2_1P2_0P1_7P1_6P1_5P1_4P1_3P1_2P1_1P1_0P0_7P0_6P0_5P0_4P0_3P0_2P0_1P0_0P10_7P10_6P10_5P10_4P10_3P10_2P10_1P10_0
KI3KI2KI1KI0
AN0_7AN0_6AN0_5AN0_4AN0_3AN0_2AN0_1AN0_0AN7AN6AN5AN4AN3AN2AN1AN0
INT4INT3
Pin No.
Control Pin
FPGP
5152535556575859606162636566676869707172737475767778798081828384858687809192939495969799100
49505152535556575859
60VCC261
62VSS63656667686970717273747576777879808182838485868780919293
94AVSS9596VREF97AVCC98
Interrupt PinTimer PinUART PinAnalog PinBus Control Pin
A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0
P9_7ADTRG
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M16C/30P Group
1. Overview
1.6Pin Description
Pin Description (1)
Pin NameVCC1, VCC2VSSAVCCAVSSRESETCNVSS
I/O TypeDescription
IApply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 = VCC2.IApplies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.IThe microcomputer is in a reset state when applying “L” to the this
pin.ISwitches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode.ISwitches the data bus in external memory space. The data bus is
16 bits long when the this pin is held \"L\" and 8 bits long when the this pin is held \"H\". Set it to either one. Connect this pin to VSS when an single-chip mode.
I/OInputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
I/OInputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
OOutput address bits (A0 to A19).
OO
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program.• WRL, WRH and RD are selected
The WRL signal becomes \"L\" by writing data to an even address in an external memory space.
The WRH signal becomes \"L\" by writing data to an odd address in an external memory space.
The RD pin signal becomes \"L\" by reading data in an external memory space.
• WR, BHE and RD are selected
The WR signal becomes \"L\" by writing data in an external memory space. The RD signal becomes \"L\" by reading data in an external memory space.The BHE signal becomes \"L\" by accessing an odd address.Select WR, BHE and RD for an external 8-bit data bus.ALE is a signal to latch the address.
While the HOLD pin is held \"L\hold state.
In a hold state, HLDA outputs a \"L\" signal.
While applying a \"L\" signal to the RDY pin, the microcomputer is placed in a wait state.
Table 1.8
Signal NamePower supply inputAnalog power supply inputReset inputCNVSS
External data bus width select input
BYTE
Bus control pinsD0 to D7D8 to D15A0 to A19CS0 to CS3WRL/WRWRH/BHERD
ALEHOLDHLDARDY
OIOI
I : Input O : Output I/O : Input and output
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M16C/30P Group
1. Overview
Table 1.9
Signal NameMain clock input
Main clock outputSub clock input
Sub clock output
Clock outputINT interrupt inputNMI interrupt input
Key input interrupt inputTimer A
Pin Description (2)
Pin NameXINXOUTXCINXCOUTCLKOUTINT0 to INT4NMI KI0 to KI3TA0OUT to TA2OUT
TA0IN to TA2INTB0IN to TB2INCTS0 to CTS2RTS0 to RTS2 CLK0 to CLK2RXD0 to RXD2TXD0 to TXD2CLKS1
SDA0 to SDA2SCL0 to SCL2
I/O Type
I
OIOOIIII/OIIIOI/OIOOI/OI/OIIII/OII/O
Description
I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To use the external clock, input the clock from XIN and leave XOUT open.I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To use the external clock, input the clock from XCIN and leave XCOUT open.
The clock of the same cycle as fC, f8, or f32 is outputted.Input pins for the INT interrupt.Input pin for the NMI interrupt.Input pins for the key input interrupt.
These are timer A0 to timer A2 I/O pins. (however, the output of TA0OUT for the N-channel open drain output.)These are timer A0 to timer A2 input pins.These are timer B0 to timer B2 input pins.These are send control input pins.These are receive control output pins.
These are transfer clock I/O pins.These are serial data input pins.
These are serial data output pins. (however, TXD2 for the N-channel open drain output.)
This is output pin for transfer clock output from multiple pins function.These are serial data I/O pins. (however, SDA2 for the N-channel open drain output.)
These are transfer clock I/O pins. (however, SCL2 for the N-channel open drain output.)
Applies the reference voltage for the A/D converter.Analog input pins for the A/D converter.This is an A/D trigger input pin.
This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
8-bit I/O ports in CMOS, having a direction register to select an input or output.
Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (however, P7_0 and P7_1 for the N-channel open drain output.)
Timer BSerial interface
I2C mode
Reference voltage inputA/D converter
VREF
AN0 to AN7, AN0_0 to AN0_7ADTRGANEX0ANEX1
P0_0 to P0_7,P1_0 to P1_7,P2_0 to P2_7,P3_0 to P3_7,P4_0 to P4_7,P5_0 to P5_7,P6_0 to P6_7,P7_0 to P7_7,P9_0 to P9_7,P10_0 to P10_7P8_0 to P8_4, P8_6, P8_7P8_5
I/O port
I/OI
I/O ports having equivalent functions to P0.
Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register.
Input port
I : Input O : Output I/O : Input and output
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M16C/30P Group
2. Central Processing Unit (CPU)
2.Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise aregister bank. There are two register banks.
b31b15b8b7b0R2R3R0HR1HR2R3A0A1FBb19R0LR1LData Registers (1)Address Registers (1)Frame Base Registers (1)b0b15INTBHINTBLInterrupt Table Registerb19b0PCb15b0Program CounterUSPISPSBb15b0User Stack PointerInterrupt Stack PointerStatic Base RegisterFLGb15b8b7b0Flag RegisterIPLUIOBSZDCCarry FlagDebug FlagZero FlagSign FlagRegister Bank Select FlagOverflow FlagInterrupt Enable FlagStack Pointer Select FlagReserved AreaProcessor Interrupt Priority LevelReserved AreaNOTES:1. These registers comprise a register bank. There are two register banks.Figure 2.1Central Processing Unit Register2.1Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 arethe same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit dataregister (R2R0). R3R1 is the same as R2R0.
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M16C/30P Group
2. Central Processing Unit (CPU)
2.2Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relativeaddressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flagis cleared to “0” when the interrupt request is accepted.
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M16C/30P Group
2. Central Processing Unit (CPU)
2.8.8Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for softwareinterrupt Nos. 0 to 31 is executed.
2.8.9Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
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M16C/30P Group
3. Memory
3.Memory
Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h toFFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a -Kbyteinternal ROM is allocated to the addresses from F0000h to FFFFFh.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the startaddress of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 5-Kbyteinternal RAM is allocated to the addresses from 00400h to 017FFh. In addition to storing data, the internal RAM alsostores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addressesfrom 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has nofunctions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPSor JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
00000hSFR00400hInternal RAMXXXXXhReserved area (1)0F000hInternal ROM(data area) (3, 4)0FFFFh10000hExternal area27000hReserved areaInternal RAMSize5 Kbytes6 Kbytes12 KbytesAddress XXXXXh017FFh01BFFh033FFhSize96 Kbytes128 Kbytes160 Kbytes192 Kbytes256 KbytesInternal ROM (5)Address YYYYYhE8000hE0000hD8000hD0000hC0000h(6)FFE00hSpecial pagevector tableFFFDCh28000hExternal areaD0000hReserved area (2, 4)YYYYYhInternal ROM(program area) (5)FFFFFhFFFFFhUndefined instructionOverflowBRK instructionAddress matchSingle stepWatchdog timerDBCNMIResetNOTES:1.During memory expansion and microprocessor modes, can be used.2.In memory expansion mode, can be used.3.As for the flash memory version, 4-Kbyte space (block A) exists.4.Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1” .5.When using the masked ROM version, write nothing to internal ROM area.6.When the PM13 bit is set to \"0he PM13 bit is set to \"1\Figure 3.1Memory MapRev.1.22Mar 30, 2007REJ03B0088-0122
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M16C/30P Group
4. Special Function Register (SFR)
4.Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFRinformation.Table 4.1
Address0000h0001h0002h0003h0004h0005h0006h0007h0008h0009h000Ah000Bh000Ch000Dh000Eh000Fh0010h0011h0012h0013h0014h0015h0016h0017h0018h0019h001Ah001Bh001Ch001Dh001Eh001Fh0020h0021h0022h0023h0024h0025h0026h0027h0028h0029h002Ah002Bh002Ch002Dh002Eh002Fh0030h0031h0032h0033h0034h0035h0036h0037h0038h0039h003Ah003Bh003Ch003Dh003Eh003FhSFR Information (1) (1)
RegisterSymbolAfter ResetProcessor Mode Register 0 (2)Processor Mode Register 1System Clock Control Register 0System Clock Control Register 1Chip Select Control Register Address Match Interrupt Enable RegisterProtect RegisterPM0PM1CM0CM1CSRAIERPRCR00000000b(CNVSS pin is “L”)00000011b(CNVSS pin is “H”)
00XXX0X0b01001000b00100000b00000001bXXXXXX00bXX000000bWatchdog Timer Start RegisterWatchdog Timer Control RegisterAddress Match Interrupt Register 0WDTSWDCRMAD0XXh00XXXXXXb00h00hX0h00h00hX0h
Address Match Interrupt Register 1RMAD1DMA0 Source PointerSAR0XXhXXhXXhXXhXXhXXhXXhXXh
DMA0 Destination PointerDAR0DMA0 Transfer CounterTCR0DMA0 Control RegisterDM0CON00000X00bDMA1 Source PointerSAR1XXhXXhXXhXXhXXhXXhXXhXXh
DMA1 Destination PointerDAR1DMA1 Transfer CounterTCR1DMA1 Control RegisterDM1CON00000X00bNOTES:
1.The blank areas are reserved and cannot be accessed by users.2.The PM00 and PM01 bits do not change at software reset.X : Nothing is mapped to this bit
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M16C/30P Group
Table 4.2
Address0040h0041h0042h0043h0044h0045h0046h0047h0048h0049h004Ah004Bh004Ch004Dh004Eh004Fh0050h0051h0052h0053h00h0055h0056h0057h0058h0059h005Ah005Bh005Ch005Dh005Eh005Fh0060h to01AFh01B0h01B1h01B2h01B3h01B4h01B5h01B6h01B7h01B8h01B9h01BAh01BBh01BCh01BDh01BEh01BFh01C0h to024Fh0250h0251h0252h0253h02h0255h0256h0257h0258h0259h025Ah025Bh025Ch025Dh025Eh025Fh0260h to033Fh
4. Special Function Register (SFR)
SFR Information (2) (1)
RegisterSymbolAfter ResetINT3 Interrupt Control RegisterUART1 BUS Collision Detection Interrupt Control RegisterUART0 BUS Collision Detection Interrupt Control RegisterINT4 Interrupt Control RegisterUART2 Bus Collision Detection Interrupt Control RegisterDMA0 Interrupt Control RegisterDMA1 Interrupt Control RegisterKey Input Interrupt Control RegisterA/D Conversion Interrupt Control RegisterUART2 Transmit Interrupt Control RegisterUART2 Receive Interrupt Control RegisterUART0 Transmit Interrupt Control RegisterUART0 Receive Interrupt Control RegisterUART1 Transmit Interrupt Control RegisterUART1 Receive Interrupt Control RegisterTimer A0 Interrupt Control RegisterTimer A1 Interrupt Control RegisterTimer A2 Interrupt Control RegisterINT3ICU1BCNICU0BCNICINT4ICBCNICDM0ICDM1ICKUPICADICS2TICS2RICS0TICS0RICS1TICS1RICTA0ICTA1ICTA2ICXX00X000bXXXXX000bXXXXX000bXX00X000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bXXXXX000bTimer B0 Interrupt Control RegisterTimer B1 Interrupt Control RegisterTimer B2 Interrupt Control RegisterINT0 Interrupt Control RegisterINT1 Interrupt Control RegisterINT2 Interrupt Control RegisterTB0ICTB1ICTB2ICINT0ICINT1ICINT2ICXXXXX000bXXXXX000bXXXXX000bXX00X000bXX00X000bXX00X000bFlash Memory Control Register 1 (2)FMR10X00XX0Xb00000001bFlash Memory Control Register 0 (3) FMR0Peripheral Clock Select RegisterPCLKR00000011bNOTES:
1.The blank areas are reserved and cannot be accessed by users.2.This register is included in the flash memory version.
3.This register is included in the flash memory version and one time flash version. X : Nothing is mapped to this bit
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M16C/30P Group
Table 4.3
Address0340h0341h0342h0343h0344h0345h0346h0347h0348h0349h034Ah034Bh034Ch034Dh034Eh034Fh0350h0351h0352h0353h03h0355h0356h0357h0358h0359h035Ah035Bh035Ch035Dh035Eh035Fh0360h0361h0362h0363h03h0365h0366h0367h0368h0369h036Ah036Bh036Ch036Dh036Eh036Fh0370h0371h0372h0373h0374h0375h0376h0377h0378h0379h037Ah037Bh037Ch037Dh037Eh037Fh
4. Special Function Register (SFR)
SFR Information (3) (1)
RegisterSymbolAfter ResetInterrupt Factor Select Register 2Interrupt Factor Select RegisterIFSR2AIFSR00XXXXXXb00hUART0 Special Mode Register 4UART0 Special Mode Register 3UART0 Special Mode Register 2UART0 Special Mode RegisterUART1 Special Mode Register 4UART1 Special Mode Register 3UART1 Special Mode Register 2UART1 Special Mode RegisterUART2 Special Mode Register 4UART2 Special Mode Register 3UART2 Special Mode Register 2UART2 Special Mode RegisterUART2 Transmit/Receive Mode RegisterUART2 Bit Rate GeneratorUART2 Transmit Buffer RegisterUART2 Transmit/Receive Control Register 0UART2 Transmit/Receive Control Register 1UART2 Receive Buffer RegisterU0SMR4U0SMR3U0SMR2U0SMRU1SMR4U1SMR3U1SMR2U1SMRU2SMR4U2SMR3U2SMR2U2SMRU2MRU2BRGU2TBU2C0U2C1U2RB00h000X0X0XbX0000000bX0000000b00h000X0X0XbX0000000bX0000000b00h000X0X0XbX0000000bX0000000b00hXXhXXhXXh
00001000b00000010bXXhXXh
NOTES:
1.The blank areas are reserved and cannot be accessed by users.X : Nothing is mapped to this bit
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M16C/30P Group
Table 4.4
Address0380h0381h0382h0383h0384h0385h0386h0387h0388h03h038Ah038Bh038Ch038Dh038Eh038Fh0390h0391h0392h0393h0394h0395h0396h0397h0398h0399h039Ah039Bh039Ch039Dh039Eh039Fh03A0h03A1h03A2h03A3h03A4h03A5h03A6h03A7h03A8h03A9h03AAh03ABh03ACh03ADh03AEh03AFh03B0h03B1h03B2h03B3h03B4h03B5h03B6h03B7h03B8h03B9h03BAh03BBh03BCh03BDh03BEh03BFh4. Special Function Register (SFR)
SFR Information (4) (1)
RegisterCount Start FlagClock Prescaler Reset FagOne-Shot Start FlagTrigger Select RegisterUp-Down FlagTimer A0 RegisterTimer A1 RegisterTimer A2 RegisterSymbolTABSRCPSRFONSFTRGSRUDFTA0TA1TA2After Reset000XX000b0XXXXXXXb00XXX000bXXXX0000bXX0XX000b (2)XXhXXhXXhXXhXXhXXh
Timer B0 RegisterTimer B1 RegisterTimer B2 RegisterTimer A0 Mode RegisterTimer A1 Mode RegisterTimer A2 Mode RegisterTB0TB1TB2TA0MRTA1MRTA2MRXXhXXhXXhXXhXXhXXh00h00h00hTimer B0 Mode RegisterTimer B1 Mode RegisterTimer B2 Mode RegisterTB0MRTB1MRTB2MR00XX0000b00XX0000b00XX0000bUART0 Transmit/Receive Mode RegisterUART0 Bit Rate GeneratorUART0 Transmit Buffer RegisterUART0 Transmit/Receive Control Register 0UART0 Transmit/Receive Control Register 1UART0 Receive Buffer RegisterUART1 Transmit/Receive Mode RegisterUART1 Bit Rate GeneratorUART1 Transmit Buffer RegisterUART1 Transmit/Receive Control Register 0UART1 Transmit/Receive Control Register 1UART1 Receive Buffer RegisterUART Transmit/Receive Control Register 2U0MRU0BRGU0TBU0C0U0C1U0RBU1MRU1BRGU1TBU1C0U1C1U1RBUCON00hXXhXXhXXh
00001000b00000010bXXhXXh00hXXhXXhXXh
00001000b00000010bXXhXXh
X0000000bDMA0 Request Factor Select RegisterDMA1 Request Factor Select RegisterCRC Data RegisterCRC Input RegisterDM0SLDM1SLCRCDCRCIN00h00hXXhXXhXXhNOTES:
1.The blank areas are reserved and cannot be accessed by users.
2.Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.X : Nothing is mapped to this bit
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M16C/30P Group
Table 4.5
Address03C0h03C1h03C2h03C3h03C4h03C5h03C6h03C7h03C8h03C9h03CAh03CBh03CCh03CDh03CEh03CFh03D0h03D1h03D2h03D3h03D4h03D5h03D6h03D7h03D8h03D9h03DAh03DBh03DCh03DDh03DEh03DFh03E0h03E1h03E2h03E3h03E4h03E5h03E6h03E7h03E8h03E9h03EAh03EBh03ECh03EDh03EEh03EFh03F0h03F1h03F2h03F3h03F4h03F5h03F6h03F7h03F8h03F9h03FAh03FBh03FCh03FDh03FEh03FFh4. Special Function Register (SFR)
SFR Information (5) (1)
RegisterSymbolAD0AD1AD2AD3AD4AD5AD6AD7XXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXhXXh
After ResetA/D Register 0A/D Register 1A/D Register 2A/D Register 3A/D Register 4A/D Register 5A/D Register 6A/D Register 7A/D Control Register 2A/D Control Register 0A/D Control Register 1ADCON2ADCON0ADCON1XXX000X0b000X0XXXb00000XXXbPort P0 RegisterPort P1 RegisterPort P0 Direction RegisterPort P1 Direction RegisterPort P2 RegisterPort P3 RegisterPort P2 Direction RegisterPort P3 Direction RegisterPort P4 RegisterPort P5 RegisterPort P4 Direction RegisterPort P5 Direction RegisterPort P6 RegisterPort P7 RegisterPort P6 Direction RegisterPort P7 Direction RegisterPort P8 RegisterPort P9 RegisterPort P8 Direction RegisterPort P9 Direction RegisterPort P10 RegisterPort P10 Direction RegisterP0P1PD0PD1P2P3PD2PD3P4P5PD4PD5P6P7PD6PD7P8P9PD8PD9P10PD10XXhXXh00h00hXXhXXh00h00hXXhXXh00h00hXXhXXh00h00hXXhXXh00X00000b00hXXh00hPull-Up Control Register 0Pull-Up Control Register 1Pull-Up Control Register 2Port Control RegisterPUR0PUR1PUR2PCR00h00000000b (2)00000010b (2)00h00hNOTES:
1.The blank areas are reserved and cannot be accessed by users.2.At hardware reset, the register is as follows:
• “00000000b” where “L” is inputted to the CNVSS pin• “00000010b” where “H” is inputted to the CNVSS pinAt software reset, the register is as follows:
• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).
• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode).X : Nothing is mapped to this bit
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M16C/30P Group
5. Electrical Characteristics
5.Electrical Characteristics
Table 5.1
SymbolVCCAVCCVI
Analog Supply VoltageInput Voltage
RESET, CNVSS, BYTE,
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,P9_0 to P9_7, P10_0 to P10_7,VREF, XINP7_0, P7_1
VO
Output Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,XOUTP7_0, P7_1
PdTopr
Power DissipationOperating Ambient Temperature
When the Microcomputer is Operating
One Time Flash Program EraseFlash Program Erase
Tstg
Storage Temperature
−40°C Parameter Supply Voltage(VCC1=VCC2) ConditionVCC1=VCC2=AVCCVCC1=VCC2=AVCC Rated Value−0.3 to 6.5−0.3 to 6.5−0.3 to VCC+0.3 UnitVVV −0.3 to 6.5−0.3 to VCC+0.3 VV −0.3 to 6.5 300 −20 to 85 / −40 to 85 0 to 600 to 60−65 to 150 VmW°C °C Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 23 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.2 SymbolVCCAVCCVSSAVSSVIH Recommended Operating Conditions (1) Parameter Supply Voltage (VCC1=VCC2)Analog Supply VoltageSupply VoltageAnalog Supply VoltageHIGH Input Voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0(during single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode)P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTEP7_0, P7_1 Standard Min.2.7 Typ.5.0VCC00 0.8VCC0.8VCC0.5VCC0.8VCC0.8VCC 0000 VCCVCCVCCVCC6.50.2VCC0.2VCC0.16VCC0.2VCC−10.0−5.010.05.0 00 32.768 0 1620×VCC1−44 5016Max.5.5 UnitVVVVVVVVVVVVVmAmAmAmAMHzMHzkHzMHz VIL LOW Input Voltage P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0(during single-chip mode) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (data input during memory expansion and microprocessor mode)P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, XIN, RESET, CNVSS, BYTE IOH(peak)IOH(avg)IOL(peak)IOL(avg)f(XIN) HIGH Peak Output CurrentHIGH Average Output CurrentLOW Peak Output CurrentLOW Average Output Current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 Main Clock Input VCC=3.0V to 5.5VOscillation VCC=2.7V to 3.0V (4)Frequency Sub-Clock Oscillation FrequencyCPU Operation Clock f(XCIN)f(BCLK) NOTES: 1.Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.2.The Average Output Current is the mean value within 100ms. 3.The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9 and P10 must be 80mA max. The total IOL(peak) for ports P3, P4, P5, P6, P7 and P8_0 to P8_4 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must be −40mA max. The total IOH(peak) for ports P3, P4 and P5 must be −40mA max. The total IOH(peak) for ports P6, P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7 and P9 must be −40mA max. Set Average Output Current to 1/2 of peak.4.Relationship between main clock oscillation frequency, and supply voltage. Main clock input oscillation frequencyf(XIN) operating maximum frequency [MHz]20 x VCC1-44MHz16.010.00.02.73.05.5VCC1[V] (main clock: no division)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 24 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.3 Symbol−INL A/D Conversion Characteristics (1) Parameter Resolution Integral Non-Linearity Error 10bit Measuring Condition VREF=VCCVREF=VCC=5VVREF=VCC=3.3V 8bit AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 inputAN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 inputAN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 inputAN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input 3 ±2±5±5 VREF=VCC VREF=VCC=5V, φAD=10MHzVREF=VCC=5V, φAD=10MHz 103.32.80.33.00 VCCVREF40 Standard Min. Typ. Max.10±5 UnitBitsLSB ±7LSB VREF=VCC=5V, 3.3VVREF=VCC=5VVREF=VCC=3.3V ±2±5 LSBLSB −Absolute Accuracy10bit ±7LSB 8bit −DNL−−RLADDERtCONVtCONVtSAMPVREFVIA Tolerance Level ImpedanceDifferential Non-Linearity ErrorOffset ErrorGain ErrorLadder Resistance 10-bit Conversion Time, Sample & Hold Function Available 8-bit Conversion Time, Sample & Hold Function AvailableSampling TimeReference VoltageAnalog Input Voltage VREF=VCC=5V, 3.3V±2LSBkΩLSBLSBLSBkΩμsμsμsVV NOTES: 1.Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2.φAD frequency must be 10 MHz or less. 3.When sample & hold function is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.4.When sample & hold function is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2. Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 25 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.4 Symbol−−−−−−−tPS− Flash Memory Version Electrical Characteristics (1) Parameter Program and Erase Endurance (2)Word Program Time (VCC1=5.0V)Lock Bit Program Time Block Erase Time(VCC1=5.0V) 4-Kbyte block8-Kbyte block32-Kbyte block-Kbyte block Flash Memory Circuit Stabilization Wait TimeData Hold Time (4) 10 Standard Min.100(3) 25250.30.30.50.8 200200444415 Typ. Max. Unitcycleμsμsssssμsyear NOTES: 1.Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified.2.Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is 100, each block can be erased 100 times. For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 3.Maximum number of E/W cycles for which operation is guaranteed.4.Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5). Table 5.5 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics Flash Read Operation VoltageVCC1=2.7 to 5.5 V (Topr = -40°C to 85°C (U3) -20°C to 85°C (U5)) Flash Program, Erase VoltageVCC1 = 3.3 ± 0.3 V or 5.0 ± 0.5 (Topr = 0°C to 60°C ) Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 26 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.6 Symbol−−tPS− One Time Flash Version Electrical Characteristics (1) Parameter Program Endurance Word Program Time (VCC1=5.0V) One Time Flash Memory Circuit Stabilization Wait TimeData Hold Time (4) 10 50Standard Min. Typ. Max.150015 Unitcycleμsμsyear NOTES: 1.Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified.2.Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5). Table 5.7One Time Flash Version Program Voltage and Read Operation Voltage CharacteristicsFlash Read Operation VoltageVCC1=2.7 to 5.5 V (Topr = -40°C to 85°C (U3) -20°C to 85°C (U5)) Flash Program VoltageVCC1 = 3.3 ± 0.3 V or 5.0 ± 0.5 (Topr = 0°C to 60°C ) Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 27 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.8 Symboltd(P-R)td(R-S)td(W-S) Power Supply Circuit Timing Characteristics Parameter Time for Internal Power Supply Stabilization During Powering-OnSTOP Release Time Low Power Dissipation Mode Wait Mode Release Time Measuring ConditionVCC=2.7V to 5.5V Standard Min. Typ. Max.215001500 Unitmsμsμs td(P-R)Time for Internal PowerSupply Stabilization DuringPowering-OnRecommendedoperation voltageVCCCPU clocktd(P-R)td(R-S)STOP Release Timetd(W-S)Low Power DissipationMode Wait Mode ReleaseTimeInterrupt for(a) Stop mode releaseor(b)Wait mode releaseCPU clock(a)(b)td(R-S)td(W-S)Figure 5.1Power Supply Circuit Timing Diagram Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 28 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Table 5.9 SymbolVOH HIGH Output VoltageHIGH Output Voltage Electrical Characteristics(1) (1) Parameter Measuring Condition StandardMin.VCC−2.0 Typ. Max.VCC Unit IOH=−5mAP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH=−200μAP3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGHPOWERLOWPOWERHIGHPOWERLOWPOWER IOH=−1mAIOH=−0.5mAWith no load appliedWith no load appliedIOL=5mA V VOH VCC−0.3VCC−2.0VCC−2.0 2.51.6 VCCVCCVCC V VOHHIGH Output Voltage XOUTHIGH Output Voltage XCOUT VV VOL LOW Output VoltageLOW Output Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGHPOWERLOWPOWERHIGHPOWERLOWPOWER 2.0 IOL=200μA V VOL 0.45 IOL=1mAIOL=0.5mA With no load appliedWith no load applied V VOLLOW Output Voltage XOUTLOW Output Voltage XCOUT 2.02.000 0.20.2 1.02.5 VV VT+-VT-Hysteresis TA0IN to TA2IN, TB0IN to TB2IN, INT0 to INT4, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2RESET VI=5V VV VT+-VT-IIH Hysteresis HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTELOW Input Current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE 5.0μA IILVI=0V −5.0μA RPULLUPPull-Up Resistance P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=0VP3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 30501.515 170kΩMΩMΩV RfXINRfXCINVRAM Feedback Resistance XINFeedback Resistance XCINRAM Retention Voltage At stop mode 2.0 NOTES: 1.Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN) =16MHz unless otherwise specified.Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 29 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.10 SymbolICC Electrical Characteristics (2) (1) Parameter Measuring Condition f(XIN)=16MHzNo divisionf(XIN)=16MHz, No divisionf(XIN)=16MHz, No divisionf(XIN)=10MHz, VCC1=5.0V StandardMin. Typ.1010121515252525 Max.151818 UnitmAmAmAmAmAmAμAμAμAμAμAμAμA Power Supply CurrentMask ROMIn single-chip (VCC1=VCC2=4.0V to 5.5V)mode, the output pins are open and One Time other pins are VSSFlash Flash Memory One Time Flash Flash Memory f(XIN)=10MHz, VCC1=5.0VProgram Flash Memory f(XIN)=10MHz, VCC1=5.0VEraseMask ROMOne Time Flash f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) 3502207.52.00.8 3.0 Flash Memory f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) Mask ROMOne Time FlashFlash Memory f(XCIN)=32kHzWait mode (2), Oscillation capability Highf(XCIN)=32kHzWait mode (2), Oscillation capability LowStop mode Topr =25°C μA NOTES: 1.Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=16MHz unless otherwise specified. 2.With one timer operated using fC32. 3.This indicates the memory in which the program to be executed exists. Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 30 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.11 Symboltctw(H)tw(L)trtf External Clock Input (XIN input) (1) Parameter External Clock Input Cycle TimeExternal Clock Input HIGH Pulse WidthExternal Clock Input LOW Pulse WidthExternal Clock Rise TimeExternal Clock Fall Time StandardMin.62.52525 1515Max. Unitnsnsnsnsns NOTES: 1.The condition is VCC1=VCC2=3.0 to 5.0V. Table 5.12 Symboltac1(RD-DB)tac2(RD-DB)tsu(DB-RD)tsu(RDY-BCLK)th(RD-DB)th(BCLK-RDY)th(BCLK-HOLD) Memory Expansion Mode and Microprocessor Mode Parameter Data Input Access Time (for setting with no wait)Data Input Access Time (for setting with wait)Data Input Setup TimeRDY Input Setup TimeData Input Hold TimeRDY Input Hold TimeHOLD Input Hold Time 403040000 StandardMin. Max.(NOTE 1)(NOTE 2) Unitnsnsnsnsnsnsnsns tsu(HOLD-BCLK)HOLD Input Setup Time NOTES: 1.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–45[ns]f(BCLK) 2.Calculated according to the BCLK frequency as follows: 9 (n–0.5)x10 ------------------------------------–45[ns]f(BCLK) n is ”2” for 1-wait setting. Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 31 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.13 Symboltc(TA)tw(TAH)tw(TAL) TAiIN Input Cycle TimeTAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width Timer A Input (Counter Input in Event Counter Mode) Parameter StandardMin.1004040 Max. Unitnsnsns Table 5.14 Symboltc(TA)tw(TAH)tw(TAL) Timer A Input (Gating Input in Timer Mode) Parameter TAiIN Input Cycle TimeTAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width StandardMin.400200200 Max. Unitnsnsns Table 5.15 Symboltc(TA)tw(TAH)tw(TAL) Timer A Input (External Trigger Input in One-shot Timer Mode) Parameter TAiIN Input Cycle TimeTAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width StandardMin.200100100 Max. Unitnsnsns Table 5.16 Symboltw(TAH)tw(TAL) Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Parameter TAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width StandardMin.100100 Max. Unitnsns Table 5.17 Symboltc(UP)tw(UPH)tw(UPL)tsu(UP-TIN)th(TIN-UP) Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Parameter TAiOUT Input Cycle TimeTAiOUT Input HIGH Pulse WidthTAiOUT Input LOW Pulse WidthTAiOUT Input Setup TimeTAiOUT Input Hold Time StandardMin.200010001000400400 Max. Unitnsnsnsnsns Table 5.18 Symboltc(TA) tsu(TAIN-TAOUT)tsu(TAOUT-TAIN) Timer A Input (Two-phase Pulse Input in Event Counter Mode) Parameter TAiIN Input Cycle TimeTAiOUT Input Setup TimeTAiIN Input Setup Time StandardMin.800200200 Max. Unitnsnsns Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 32 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.19 Symboltc(TB)tw(TBH)tw(TBL)tc(TB)tw(TBH)tw(TBL) Timer B Input (Counter Input in Event Counter Mode) Parameter TBiIN Input Cycle Time (counted on one edge)TBiIN Input HIGH Pulse Width (counted on one edge)TBiIN Input LOW Pulse Width (counted on one edge)TBiIN Input Cycle Time (counted on both edges)TBiIN Input HIGH Pulse Width (counted on both edges)TBiIN Input LOW Pulse Width (counted on both edges) StandardMin.10040402008080 Max. Unitnsnsnsnsnsns Table 5.20 Symboltc(TB)tw(TBH)tw(TBL) Timer B Input (Pulse Period Measurement Mode) Parameter TBiIN Input Cycle TimeTBiIN Input HIGH Pulse WidthTBiIN Input LOW Pulse Width StandardMin.400200200 Max. Unitnsnsns Table 5.21 Symboltc(TB)tw(TBH)tw(TBL) Timer B Input (Pulse Width Measurement Mode) Parameter TBiIN Input Cycle TimeTBiIN Input HIGH Pulse WidthTBiIN Input LOW Pulse Width StandardMin.400200200 Max. Unitnsnsns Table 5.22 Symboltc(AD)tw(ADL) A/D Trigger Input Parameter ADTRG Input Cycle TimeADTRG input LOW Pulse Width StandardMin.1000125 Max. Unitnsns Table 5.23 Symboltc(CK)tw(CKH)tw(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D) Serial Interface Parameter CLKi Input Cycle TimeCLKi Input HIGH Pulse WidthCLKi Input LOW Pulse WidthTXDi Output Delay TimeTXDi Hold TimeRXDi Input Setup TimeRXDi Input Hold Time 07090 StandardMin.200100100 80Max. Unitnsnsnsnsnsnsns Table 5.24 Symboltw(INH)tw(INL) External Interrupt INTi Input Parameter INTi Input HIGH Pulse WidthINTi Input LOW Pulse Width StandardMin.250250 Max. Unitnsns Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 33 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.25 Symboltd(BCLK-AD)th(BCLK-AD)th(RD-AD)th(WR-AD)td(BCLK-CS)th(BCLK-CS)td(BCLK-ALE)th(BCLK-ALE)td(BCLK-RD)th(BCLK-RD)td(BCLK-WR)th(BCLK-WR)td(BCLK-DB)th(BCLK-DB)td(DB-WR)th(WR-DB)td(BCLK-HLDA) Memory Expansion and Microprocessor Modes (for setting with no wait) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK)Address Output Hold Time (in relation to RD)Address Output Hold Time (in relation to WR)Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK)ALE Signal Output Delay TimeALE Signal Output Hold TimeRD Signal Output Delay TimeRD Signal Output Hold TimeWR Signal Output Delay TimeWR Signal Output Hold Time Data Output Delay Time (in relation to BCLK)Data Output Hold Time (in relation to BCLK) (3)Data Output Delay Time (in relation to WR)Data Output Hold Time (in relation to WR) (3)HLDA Output Delay Time 4(NOTE 1)(NOTE 2) 40 0 40 See Figure 5.2 −4 25 0 25 −3 15 −30(NOTE 2) 25 StandardMin. Max.25 Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns NOTES: 1.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–40[ns]f(BCLK) is 12.5MHz or less.f(BCLK) 2.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–10[ns]f(BCLK) 3.This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up(pull-down) resistance value. Hold time of data bus is expressed int = −CR X ln (1−VOL / VCC1)by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold timeof output ”L” level is t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)= 6.7ns. RDBiCP0P1P2P3P4P5P6P7P8P9P1030pFFigure 5.2Ports P0 to P10 Measurement CircuitRev.1.22Mar 30, 2007REJ03B0088-0122 Page 34 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.26 Symboltd(BCLK-AD)th(BCLK-AD)th(RD-AD)th(WR-AD)td(BCLK-CS)th(BCLK-CS)td(BCLK-ALE)th(BCLK-ALE)td(BCLK-RD)th(BCLK-RD)td(BCLK-WR)th(BCLK-WR)td(BCLK-DB)th(BCLK-DB)td(DB-WR)th(WR-DB)td(BCLK-HLDA) Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK)Address Output Hold Time (in relation to RD)Address Output Hold Time (in relation to WR)Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK)ALE Signal Output Delay TimeALE Signal Output Hold TimeRD Signal Output Delay TimeRD Signal Output Hold TimeWR Signal Output Delay TimeWR Signal Output Hold Time Data Output Delay Time (in relation to BCLK)Data Output Hold Time (in relation to BCLK) (3)Data Output Delay Time (in relation to WR)Data Output Hold Time (in relation to WR)(3)HLDA Output Delay Time 4(NOTE 1)(NOTE 2) 40 0 40 See Figure 5.2 −4 25 0 25 −3 15 −30(NOTE 2) 25 StandardMin. Max.25 Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns NOTES: 1.Calculated according to the BCLK frequency as follows: 9 (n–0.5)x10------------------------------------–40[ns]n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less. f(BCLK) 2.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–10[ns]f(BCLK) 3.This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up(pull-down) resistance value. Hold time of data bus is expressed int = −CR X ln (1−VOL / VCC1)by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold timeof output ”L” level is t = −30pF X 1kΩ X In(1−0.2VCC1 / VCC1)= 6.7ns. RDBiCRev.1.22Mar 30, 2007REJ03B0088-0122 Page 35 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5VXIN inputtrtw(H)tftctw(L)tc(TA)tw(TAH)TAiIN inputtw(TAL)tc(UP)tw(UPH)TAiOUT inputtw(UPL)TAiOUT input(Up/down input)During event counter modeTAiIN input(When count on fallingedge is selected)TAiIN input(When count on risingedge is selected)Two-phase pulse input inevent counter modeTAiIN inputtsu(TAIN-TAOUT)TAiOUT inputtsu(TAOUT-TAIN)tc(TB)tw(TBH)TBiIN inputtw(TBL)tc(AD)tw(ADL)ADTRG inputtsu(TAIN-TAOUT)tsu(TAOUT-TAIN)th(TIN-UP)tsu(UP-TIN)tc(TA)Figure 5.3Timing Diagram (1)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 36 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5Vtc(CK)tw(CKH)CLKitw(CKL)th(C-Q)TXDitd(C-Q)RXDitw(INL)INTi inputtw(INH)tsu(D-C)th(C-D)Figure 5.4Timing Diagram (2)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 37 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode(Effective for setting with wait)VCC1=VCC2=5VBCLKRD(Separate bus)WR, WRL, WRH(Separate bus)RDY inputtsu(RDY−BCLK)th(BCLK−RDY)(Common to setting with wait and setting without wait)BCLKtsu(HOLD−BCLK)th(BCLK−HOLD)HOLD inputHLDA inputP0, P1, P2,P3, P4,P5_0 to P5_2(1)td(BCLK−HLDA)Hi−Ztd(BCLK−HLDA)NOTES:1. These pins are set to high-impedance regardless of the input level of the BYTE pin,PM06 bit in PM0 register.· Measuring conditions :· VCC1=VCC2=5V· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V· Output timing voltage : Determined with VOL=2.5V, VOH=2.5VFigure 5.5Timing Diagram (3)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 38 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode(For setting with no wait)Read timingBCLKtd(BCLK-CS)25ns.maxVCC1=VCC2=5Vth(BCLK-CS)−3ns.minCSitcyctd(BCLK-AD)25ns.maxth(BCLK-AD)−3ns.minADiBHEtd(BCLK-ALE)25ns.maxth(BCLK-ALE)-4ns.minth(RD-AD)0ns.minALEtd(BCLK-RD)25ns.maxth(BCLK-RD)0ns.minRDtac1(RD-DB)(0.5 × tcyc-45)ns.maxHi-ZDBitsu(DB-RD)40ns.minth(RD-DB)0ns.minWrite timingBCLKtd(BCLK-CS)25ns.maxth(BCLK-CS)−3ns.minCSitcyctd(BCLK-AD)25ns.maxth(BCLK-AD)−3ns.minADiBHEtd(BCLK-ALE)25ns.maxth(BCLK-ALE)-4ns.minth(WR-AD)(0.5 × tcyc-10)ns.mintd(BCLK-WR)25ns.maxALEth(BCLK-WR)0ns.minWR, WRL,WRHtd(BCLK-DB)40ns.maxHi-Zth(BCLK-DB)4ns.minDBitd(DB-WR)(0.5 × tcyc-40)ns.minth(WR-DB)(0.5 × tcyc-10)ns.mintcyc=1f(BCLK)Measuring conditions · VCC1=VCC2=5V · Input timing voltage : VIL=0.8V, VIH=2.0V · Output timing voltage : VOL=0.4V, VOH=2.4VFigure 5.6Timing Diagram (4)Page 39 of 53 Rev.1.22Mar 30, 2007REJ03B0088-0122 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode(for 1-wait setting and external area access)Read timingBCLKtd(BCLK-CS)25ns.maxVCC1=VCC2=5Vth(BCLK-CS)−3ns.minCSitcyctd(BCLK-AD)25ns.maxth(BCLK-AD)−3ns.minADiBHEtd(BCLK-ALE)25ns.maxth(BCLK-ALE)-4ns.minth(RD-AD)0ns.minALEtd(BCLK-RD)25ns.maxth(BCLK-RD)0ns.minRDtac2(RD-DB)(1.5 × tcyc-45)ns.maxDBiHi-Ztsu(DB-RD)40ns.minth(RD-DB)0ns.minWrite timingBCLKtd(BCLK-CS)25ns.maxth(BCLK-CS)−3ns.minCSitcyctd(BCLK-AD)25ns.maxth(BCLK-AD)−3ns.minADiBHEtd(BCLK-ALE)25ns.maxth(BCLK-ALE)-4ns.minth(WR-AD)(0.5 × tcyc-10)ns.mintd(BCLK-WR)25ns.maxALEth(BCLK-WR)0ns.minWR, WRL,WRHtd(BCLK-DB)40ns.maxHi-Zth(BCLK-DB)4ns.minDBitd(DB-WR)(0.5 × tcyc-40)ns.minth(WR-DB)(0.5 × tcyc-10)ns.mintcyc=1f(BCLK)Measuring conditions · VCC1=VCC2=5V · Input timing voltage : VIL=0.8V, VIH=2.0V · Output timing voltage : VOL=0.4V, VOH=2.4VFigure 5.7Timing Diagram (5)Page 40 of 53 Rev.1.22Mar 30, 2007REJ03B0088-0122 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Table 5.27 SymbolVOH HIGH Output Voltage Electrical Characteristics (1) (1) Parameter Measuring Condition StandardMin.VCC−0.5VCC−0.5VCC−0.5 2.51.6 0.50.50.5 00Typ. Max.VCCVCCVCC Unit P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH=−1mAP3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGHPOWERLOWPOWERHIGHPOWERLOWPOWER V VOHHIGH Output Voltage XOUTHIGH Output Voltage XCOUT IOH=−0.1mAIOH=−50μA With no load appliedWith no load applied VV VOL LOW Output Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL=1mAP3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 HIGHPOWERLOWPOWERHIGHPOWERLOWPOWER V VOLLOW Output Voltage XOUTLOW Output Voltage XCOUT IOL=0.1mAIOL=50μA With no load appliedWith no load applied VV VT+-VT-Hysteresis TA0IN to TA2IN, TB0IN to TB2IN, INT0 to INT4, NMI, ADTRG, CTS0 to CTS2, RXD0 to RXD2,CLK0 to CLK2, TA0OUT to TA2OUT, KI0 to KI3, SCL0 to SCL2, SDA0 to SDA2RESET 0.20.8V VT+-VT-IIH Hysteresis0.2(0.7)1.8V HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=3V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE4.0μA IIL LOW Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=0V P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, Current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, XIN, RESET, CNVSS, BYTE −4.0μA RPULLUPPull-Up ResistanceRfXINRfXCINVRAM P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI=0VP3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7 501003.025 500kΩMΩMΩV Feedback Resistance Feedback Resistance RAM Retention Voltage XINXCIN At stop mode 2.0 NOTES: 1.Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless otherwise specified. Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 41 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Table 5.28 SymbolICC Electrical Characteristics (2) (1) Parameter Measuring Condition f(XIN)=10MHzNo divisionf(XIN)=10MHz, No divisionf(XIN)=10MHz, No division StandardMin. Typ.88812122225 Max.111313 UnitmAmAmAmAmAmAμA Power Supply CurrentMask ROMIn single-chip (VCC1=VCC2=2.7V to 3.6V)mode, the output pins are open and One Time other pins are VSSFlash Flash Memory Flash Memory f(XIN)=10MHz, ProgramVCC1=3.0VOne Time f(XIN)=10MHz, Flash ProgramVCC1=3.0VFlash Memory f(XIN)=10MHz, EraseVCC1=3.0VMask ROM f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) Flash Memory f(XCIN)=32kHz Low power dissipation mode, RAM (3) f(XCIN)=32kHz Low power dissipation mode, Flash Memory (3) f(XCIN)=32kHzMask ROM One Time Flash Wait mode (2), Flash MemoryOscillation capability High f(XCIN)=32kHzWait mode (2), Oscillation capability LowStop modeTopr =25°C One Time Flash 25μA 350μA 25μA 420μA 6.0μA 1.80.7 3.0 μAμA NOTES: 1.Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz unless otherwise specified. 2.With one timer operated using fC32. 3.This indicates the memory in which the program to be executed exists. Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 42 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.29 Symboltctw(H)tw(L)trtf External Clock Input (XIN input) Parameter External Clock Input Cycle TimeExternal Clock Input HIGH Pulse WidthExternal Clock Input LOW Pulse WidthExternal Clock Rise TimeExternal Clock Fall Time StandardMin.(NOTE 2)(NOTE 3)(NOTE 3) (NOTE 4)(NOTE 4)Max. Unitnsnsnsnsns NOTES: 1.The condition is VCC1=VCC2=2.7 to 3.0V. 2.Calculated according to the VCC1 voltage as follows: 10–6 ---------------------------------------[ns]20×VCC1–44 3.Calculated according to the VCC1 voltage as follows: 10 ---------------------------------------×0.4[ns]20×VCC1–44 –6 4.Calculated according to the VCC1 voltage as follows: –10×VCC1+45[ns] Table 5.30 Symboltac1(RD-DB)tac2(RD-DB)tsu(DB-RD)tsu(RDY-BCLK)th(RD-DB)th(BCLK-RDY)th(BCLK-HOLD) Memory Expansion Mode and Microprocessor Mode Parameter Data Input Access Time (for setting with no wait)Data Input Access Time (for setting with wait)Data Input Setup TimeRDY Input Setup TimeData Input Hold TimeRDY Input Hold TimeHOLD Input Hold Time 504050000 StandardMin. Max.(NOTE 1)(NOTE 2) Unitnsnsnsnsnsnsnsns tsu(HOLD-BCLK)HOLD Input Setup Time NOTES: 1.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–60[ns]f(BCLK) 2.Calculated according to the BCLK frequency as follows: 9 (n–0.5)x10------------------------------------–60[ns] f(BCLK) n is ”2” for 1-wait setting. Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 43 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.31 Symboltc(TA)tw(TAH)tw(TAL) TAiIN Input Cycle TimeTAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width Timer A Input (Counter Input in Event Counter Mode) Parameter StandardMin.1506060 Max. Unitnsnsns Table 5.32 Symboltc(TA)tw(TAH)tw(TAL) Timer A Input (Gating Input in Timer Mode) Parameter TAiIN Input Cycle TimeTAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width StandardMin.600300300 Max. Unitnsnsns Table 5.33 Symboltc(TA)tw(TAH)tw(TAL) Timer A Input (External Trigger Input in One-shot Timer Mode) Parameter TAiIN Input Cycle TimeTAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width StandardMin.300150150 Max. Unitnsnsns Table 5.34 Symboltw(TAH)tw(TAL) Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Parameter TAiIN Input HIGH Pulse WidthTAiIN Input LOW Pulse Width StandardMin.150150 Max. Unitnsns Table 5.35 Symboltc(UP)tw(UPH)tw(UPL)tsu(UP-TIN)th(TIN-UP) Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Parameter TAiOUT Input Cycle TimeTAiOUT Input HIGH Pulse WidthTAiOUT Input LOW Pulse WidthTAiOUT Input Setup TimeTAiOUT Input Hold Time StandardMin.300015001500600600 Max. Unitnsnsnsnsns Table 5.36 Symboltc(TA) tsu(TAIN-TAOUT)tsu(TAOUT-TAIN) Timer A Input (Two-phase Pulse Input in Event Counter Mode) Parameter TAiIN Input Cycle TimeTAiOUT Input Setup TimeTAiIN Input Setup Time StandardMin.2500500 Max. Unitμsnsns Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 44 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.37 Symboltc(TB)tw(TBH)tw(TBL)tc(TB)tw(TBH)tw(TBL) Timer B Input (Counter Input in Event Counter Mode) Parameter TBiIN Input Cycle Time (counted on one edge)TBiIN Input HIGH Pulse Width (counted on one edge)TBiIN Input LOW Pulse Width (counted on one edge)TBiIN Input Cycle Time (counted on both edges)TBiIN Input HIGH Pulse Width (counted on both edges)TBiIN Input LOW Pulse Width (counted on both edges) StandardMin.1506060300120120 Max. Unitnsnsnsnsnsns Table 5.38 Symboltc(TB)tw(TBH)tw(TBL) Timer B Input (Pulse Period Measurement Mode) Parameter TBiIN Input Cycle TimeTBiIN Input HIGH Pulse WidthTBiIN Input LOW Pulse Width StandardMin.600300300 Max. Unitnsnsns Table 5.39 Symboltc(TB)tw(TBH)tw(TBL) Timer B Input (Pulse Width Measurement Mode) Parameter TBiIN Input Cycle TimeTBiIN Input HIGH Pulse WidthTBiIN Input LOW Pulse Width StandardMin.600300300 Max. Unitnsnsns Table 5.40 Symboltc(AD)tw(ADL) A/D Trigger Input Parameter ADTRG Input Cycle TimeADTRG Input LOW Pulse Width StandardMin.1500200 Max. Unitnsns Table 5.41 Symboltc(CK)tw(CKH)tw(CKL)td(C-Q)th(C-Q)tsu(D-C)th(C-D) Serial Interface Parameter CLKi Input Cycle TimeCLKi Input HIGH Pulse WidthCLKi Input LOW Pulse WidthTXDi Output Delay TimeTXDi Hold TimeRXDi Input Setup TimeRXDi Input Hold Time 010090 StandardMin.300150150 160Max. Unitnsnsnsnsnsnsns Table 5.42 Symboltw(INH)tw(INL) External Interrupt INTi Input Parameter INTi Input HIGH Pulse WidthINTi Input LOW Pulse Width StandardMin.380380 Max. Unitnsns Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 45 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.43 Symboltd(BCLK-AD)th(BCLK-AD)th(RD-AD)th(WR-AD)td(BCLK-CS)th(BCLK-CS)td(BCLK-ALE)th(BCLK-ALE)td(BCLK-RD)th(BCLK-RD)td(BCLK-WR)th(BCLK-WR)td(BCLK-DB)th(BCLK-DB)td(DB-WR)th(WR-DB)td(BCLK-HLDA) Memory Expansion and Microprocessor Modes (for setting with no wait) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK)Address Output Hold Time (in relation to RD)Address Output Hold Time (in relation to WR)Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK)ALE Signal Output Delay TimeALE Signal Output Hold TimeRD Signal Output Delay TimeRD Signal Output Hold TimeWR Signal Output Delay TimeWR Signal Output Hold Time Data Output Delay Time (in relation to BCLK)Data Output Hold Time (in relation to BCLK) (3)Data Output Delay Time (in relation to WR)Data Output Hold Time (in relation to WR) (3)HLDA Output Delay Time 4(NOTE 1)(NOTE 2) 40 0 40 See Figure 5.8 −4 30 0 30 0 25 00(NOTE 2) 30 StandardMin. Max.30 Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns NOTES: 1.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–40[ns]f(BCLK) is 12.5MHz or less.f(BCLK) 2.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–10[ns]f(BCLK) 3.This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up(pull-down) resistance value. Hold time of data bus is expressed int = −CR X ln (1−VOL / VCC1)by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold timeof output ”L” level is t = −30pF X 1k Ω X In(1−0.2VCC1 / VCC1)= 6.7ns. RDBiCP0P1P2P3P4P5P6P7P8P9P1030pFFigure 5.8Ports P0 to P10 Measurement CircuitRev.1.22Mar 30, 2007REJ03B0088-0122 Page 46 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)Table 5.44 Symboltd(BCLK-AD)th(BCLK-AD)th(RD-AD)th(WR-AD)td(BCLK-CS)th(BCLK-CS)td(BCLK-ALE)th(BCLK-ALE)td(BCLK-RD)th(BCLK-RD)td(BCLK-WR)th(BCLK-WR)td(BCLK-DB)th(BCLK-DB)td(DB-WR)th(WR-DB)td(BCLK-HLDA) Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK)Address Output Hold Time (in relation to RD)Address Output Hold Time (in relation to WR)Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK)ALE Signal Output Delay TimeALE Signal Output Hold TimeRD Signal Output Delay TimeRD Signal Output Hold TimeWR Signal Output Delay TimeWR Signal Output Hold Time Data Output Delay Time (in relation to BCLK)Data Output Hold Time (in relation to BCLK) (3)Data Output Delay Time (in relation to WR)Data Output Hold Time (in relation to WR)(3)HLDA Output Delay Time 4(NOTE 1)(NOTE 2) 40 0 40 See Figure 5.8 -4 30 0 30 0 25 00(NOTE 2) 30 StandardMin. Max.30 Unitnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns NOTES: 1.Calculated according to the BCLK frequency as follows: 9 (n–0.5)x10------------------------------------–40[ns]n is “1” for 1-wait setting, f(BCLK) is 12.5MHz or less. f(BCLK) 2.Calculated according to the BCLK frequency as follows: 9 0.5x10 -----------------------–10[ns]f(BCLK) 3.This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up(pull-down) resistance value. Hold time of data bus is expressed int = −CR X ln (1−VOL / VCC1)by a circuit of the right figure. For example, when VOL = 0.2VCC1, C = 30pF, R = 1kΩ, hold timeof output ”L” level is t = −30pF X 1kΩ X In(1−0.2VCC1 / VCC1)= 6.7ns. RDBiCRev.1.22Mar 30, 2007REJ03B0088-0122 Page 47 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3VXIN inputtrtw(H)tftctw(L)tc(TA)tw(TAH)TAiIN inputtw(TAL)tc(UP)tw(UPH)TAiOUT inputtw(UPL)TAiOUT input(Up/down input)During Event Counter ModeTAiIN input(When count on fallingedge is selected)TAiIN input(When count on risingedge is selected)Two-Phase Pulse Input inEvent Counter ModeTAiIN inputtsu(TAIN-TAOUT)tsu(TAIN-TAOUT)tsu(TAOUT-TAIN)tc(TA)th(TIN-UP)tsu(UP-TIN)TAiOUT inputtsu(TAOUT-TAIN)tc(TB)tw(TBH)TBiIN inputtw(TBL)tc(AD)tw(ADL)ADTRG inputFigure 5.9Timing Diagram (1)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 48 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3Vtc(CK)tw(CKH)CLKitw(CKL)th(C-Q)TXDitd(C-Q)tsu(D-C)th(C-D)RXDitw(INL)INTi inputtw(INH)Figure 5.10Timing Diagram (2)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 49 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode(Effective for setting with wait)VCC1=VCC2=3VBCLKRD(Separate bus)WR, WRL, WRH(Separate bus)RDY inputtsu(RDY−BCLK)th(BCLK−RDY)(Common to setting with wait and setting without wait)BCLKtsu(HOLD−BCLK)HOLD inputth(BCLK−HOLD)HLDA outputP0, P1, P2,P3, P4,P5_0 to P5_2 (1)td(BCLK−HLDA)Hi−Ztd(BCLK−HLDA)NOTES:1. These pins are set to high-impedance regardless of the input level of the BYTE pin,PM06 bit in PM0 register.Measuring conditions :· VCC1=VCC2=3V· Input timing voltage : Determined with VIL=0.6V, VIH=2.4V· Output timing voltage : Determined with VOL=1.5V, VOH=1.5VFigure 5.11Timing Diagram (3)Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 50 of 53 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode(for setting with no wait)Read timingVCC1=VCC2=3VBCLKtd(BCLK-CS)30ns.maxth(BCLK-CS)0ns.minCSitcyctd(BCLK-AD)30ns.maxth(BCLK-AD)0ns.minADiBHEtd(BCLK-ALE)30ns.maxth(BCLK-ALE)-4ns.minth(RD-AD)0ns.minALEtd(BCLK-RD)30ns.maxth(BCLK-RD)0ns.minRDtac1(RD-DB)(0.5 × tcyc-60)ns.maxDBiHi-Ztsu(DB-RD)50ns.minth(RD-DB)0ns.minWrite timingBCLKtd(BCLK-CS)30ns.maxth(BCLK-CS)0ns.minCSitcyctd(BCLK-AD)30ns.maxth(BCLK-AD)0ns.minADiBHEtd(BCLK-ALE)30ns.maxth(BCLK-ALE)-4ns.minth(WR-AD)(0.5 × tcyc-10)ns.minALEtd(BCLK-WR)30ns.maxth(BCLK-WR)0ns.minWR, WRL,WRHtd(BCLK-DB)40ns.maxHi-Zth(BCLK-DB)4ns.minDBitd(DB-WR)(0.5 × tcyc-40)ns.minth(WR-DB)(0.5 × tcyc-10)ns.mintcyc=1f(BCLK)Measuring conditions · VCC1=VCC2=3V · Input timing voltage : VIL=0.6V, VIH=2.4V · Output timing voltage : VOL=1.5V, VOH=1.5VFigure 5.12Timing Diagram (4)Page 51 of 53 Rev.1.22Mar 30, 2007REJ03B0088-0122 元器件交易网www.cecb2b.com M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode(for 1-wait setting and external area access)Read timingBCLKtd(BCLK−CS)30ns.maxVCC1=VCC2=3Vth(BCLK−CS)0ns.minCSitcyctd(BCLK−AD)30ns.maxth(BCLK−AD)0ns.minADiBHEtd(BCLK−ALE)30ns.maxth(BCLK−ALE)−4ns.minth(RD−AD)0ns.minALEtd(BCLK−RD)30ns.maxth(BCLK−RD)0ns.minRDtac2(RD−DB)(1.5 × tcyc−60)ns.maxDBiHi−Ztsu(DB−RD)50ns.minth(RD−DB)0ns.minWrite timingBCLKtd(BCLK−CS)30ns.maxth(BCLK−CS)0ns.minCSitcyctd(BCLK−AD)30ns.maxth(BCLK−AD)0ns.minADiBHEtd(BCLK−ALE)30ns.maxth(BCLK−ALE)−4ns.minth(WR−AD)(0.5 × tcyc−10)ns.mintd(BCLK−WR)30ns.maxALEth(BCLK−WR)0ns.minWR,WRL,WRHtd(BCLK−DB)40ns.maxHi−Zth(BCLK−DB)4ns.minDBitd(DB−WR)tcyc=1f(BCLK)(0.5 × tcyc−40)ns.minth(WR−DB)(0.5 × tcyc−10)ns.minMeasuring conditions · VCC1=VCC2=3V · Input timing voltage : VIL=0.6V, VIH=2.4V · Output timing voltage : VOL=1.5V, VOH=1.5VFigure 5.13Timing Diagram (5)Page 52 of 53 Rev.1.22Mar 30, 2007REJ03B0088-0122 元器件交易网www.cecb2b.com M16C/30P Group Appendix 1. Package Dimensions Appendix 1.Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the \"Packages\" sectionof the Renesas Technology website. JEITA Package CodeP-QFP100-14x20-0.65RENESAS CodePRQP0100JB-APrevious Code100P6S-AMASS[Typ.]1.6gHD*180D518150NOTE)1.DIMENSIONS \"*1\" AND \"*2\"DO NOT INCLUDE MOLD FLASH.2.DIMENSION \"*3\" DOES NOTINCLUDE TRIM OFFSET.*2HEEZEReferenceSymbolDimension in MillimetersMin19.813.8Nom20.014.02.822.516.522.816.823.117.13.0500.250.130°0.10.30.150.20.40.210°0.650.80.100.5750.8250.40.60.8Max20.214.2100D31EA21ZDIndex mark30FcA2HDHEAA1bpA1LDetail FcAey*3bpeyZDZEL0.5JEITA Package CodeP-LQFP100-14x14-0.50RENESAS CodePLQP0100KB-APrevious Code100P6Q-A / FP-100U / FP-100UVMASS[Typ.]0.6gHD*1D51NOTE)1.DIMENSIONS \"*1\" AND \"*2\"DO NOT INCLUDE MOLD FLASH.2.DIMENSION \"*3\" DOES NOTINCLUDE TRIM OFFSET.757650bpb1HEEReferenceSymbol*2Dimension in MillimetersMin13.913.9Nom14.014.01.415.815.816.016.016.216.21.70.050.150.10.200.180.090.1450.1250°8°0.50.080.081.01.00.350.51.00.650.200.150.25Max14.114.1c1cDETerminal cross section100A2HDZE26HEA1Index markZDF25A1bpb1cA2Ac1ceebpxA1y*3LL1Detail FxyZDZELL1Rev.1.22Mar 30, 2007REJ03B0088-0122 Page 53 of 53 元器件交易网www.cecb2b.com REVISION HISTORYM16C/30P Group Datasheet Description Rev.0.700.80 DateAug 26, 2004Mar 18, 2005 Page−−−24820212228 First Edition issued Summary development support tools -> development tools BCLK -> CPU clock Table 1.1 Performance Outline of M16C/30P GroupSerial interface is revised. Figure 1.2 Type., Memory Size, and Package is partly revised.Table 1.4 Pin Detection (2) is partly revised. Note 2 Table 5.3 A/D Conversion Characteristics is partly revised.Symbol of Table 5.4 Power Supply Circuit Timing Characteristics is partly revised. Table 5.5 Electrical Characteristics is revised.Table 5.19 Electrical Characteristics is revised. Table 1.1 Performance Outline of M16C/30P Group is partly revised.Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised.Figure 1.3 Pin Configuration is partly revised.Figure 1.4 Pin Configuration is partly revised.Tables 1.3 to 1.4 Pin Characteristics are added.Table 1.5 Pin Description is revised.3. Memory is partly revised. Table 4.1 SFR Information is partly revised.Table 4.5 SFR Information is partly revised Table 5.2 Recommended Operating Conditions is partly revised.Table 5.3 A/D Conversion Characteristics is partly revised.Note 1 is added in Table 5.6 External Clock Input (XIN input) Table 5.7 Memory Expansion Mode and Microprocessor Mode is added.Table 5.20 Memory Expansion Mode and Microprocessor Modes (for setting with no wait) is added. Figure 5.2 Ports P0 to P10 Measurement Circuit is added. Table 5.21 Memory Expansion Mode and Microprocessor Modes (for 1- to 3-wait setting and external area access) is added.Figure 5.5 Timing Diagram (3) is added.Figure 5.6 Timing Diagram (4) is added.Figure 5.7 Timing Diagram (5) is added. Note 1 to 4 are added in Table 5.23 External Clock Input (XIN input)Table 5.24 Memory Expansion Mode and Microprocessor Mode is added.Table 5.37 Memory Expansion Mode and Microprocessor Modes (for setting with no wait) is added. Figure 5.8 Ports P0 to P10 Measurement Circuit is added. Table 5.38 Memory Expansion Mode and Microprocessor Modes (for 1- to 3-wait setting and external area access) is added.Figure 5.11 Timing Diagram (3) is added. 1.00Sep 01, 200524567-14151921222528 293233343639 4043 C - 1 元器件交易网www.cecb2b.com REVISION HISTORY Rev. Date Page4445 1.10 Oct 01, 2005 245 M16C/30P Group Datasheet Description Summary Figure 5.12 Timing Diagram (4) is added.Figure 5.13 Timing Diagram (5) is added. Table 1.1 Performance Outline of M16C/30P Group is partly revised.Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised.Table 1.3 Product Code of Mask ROM version Version for M16C/30P is added. Figure 1.3 Marking Diagram of Mask ROM Version for M16C/30P is added. 661623 1.11 May 31, 2006 457 Figure 1.4 Marking Diagram of ROM -less Version for M16C/30P is added.Table 1.4 Product Code of ROM-less version for M16C/30P is added.Figure 3.1 Memory Map is partly added.Table 5.2 information is revised.1.4 Product List information is revised.Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly added. Table 1.4 Product Code of Flash Memory version and ROM-less version for M16C/30P is partly revised. Figure 1.4 Marking Diagram of Flash Memory version and ROM-less Version for M16C/30P (Top View) is partly added. 1718192326 3. Memory information is revised.Figure 3.1 Memory Map is partly revised. Table 4.1 SFR Information(1) is partly revised. Table 4.2 SFR Information(2) is partly added. Table 5.1 Absolute Maximum Ratings information is revised.Table 5.4 Flash Memory Version Electrical Characteristics is added. Table 5.5 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is added. Table 5.7 Electrical Characteristics(1) is partly deleted. Table 5.8 Electrical Characteristics (2) is partly revised. Table 5.23 Memory Expansion and Microprocessor Modes NOTES 3 is partly revised. Table 5.24 Memory Expansion and Microprocessor ModesNOTES 3 is partly revised. Table 5.25 Electrical Characteristics (1) is partly deleted. Table 5.26 Electrical Characteristics (2) is partly revised.Table 5.41 Memory Expansion and Microprocessor Modes NOTES 3 is partly revised. Table 5.42 Memory Expansion and Microprocessor ModesNOTES 3 is partly revised. 28293334404146 C - 2 元器件交易网www.cecb2b.com REVISION HISTORY Rev.1.20 DateOct 17, 2006 Page1245717192327 M16C/30P Group Datasheet Description Summary Note is partly deleted. Table 1.1 Performance Outline of M16C/30P Group is partly added.Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is added. Table 1.4 Product Code of One Time Flash version, Flash Memory ver-sion, and ROM-less version for M16C/30P is partly added.Figure 3.1 Memory Map is partly added.Table 4.2 SFR Information (2) is partly added.Table 5.1 Absolute Maximum Ratings is partly added. Table 5.6 One Time Flash Version Electrical Characteristics and Table 5.7 One Time Flash Version Program Voltage and Read Operation Voltage Characteristics is added. Table 5.10 Electrical Characteristics (2) is partly added.Table 5.28 Electrical Characteristics (2) is partly added. Table 1.4 Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P is partly revised.Table 1.2 Product List (1) is partly revised.Table 1.3 Product List (2) is partly revised.Table 4.2 SFR Information (2) is partly revised. 3042 1.211.22 Nov 02 2006Mar 30, 2007 74519 C - 3 元器件交易网www.cecb2b.com Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, JapanNotes:1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations.4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document.6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges.10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment.12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICESRefer to \"http://www.renesas.com/en/network\" for the latest and detailed information.Renesas Technology America, Inc.450 Holger Way, San Jose, CA 95134-1368, U.S.ATel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe LimitedDukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900http://www.renesas.comRenesas Technology (Shanghai) Co., Ltd.Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-78 Renesas Technology Ltd.7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Tel: <852> 2265-6688, Fax: <852> 2730-6071Renesas Technology Taiwan Co., Ltd.10th Floor, No.99, Fushing North Road, Taipei, TaiwanTel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd.1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001Renesas Technology Korea Co., Ltd.Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, KoreaTel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. BhdUnit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, MalaysiaTel: <603> 7955-9390, Fax: <603> 7955-9510© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0 因篇幅问题不能全部显示，请点此查看更多更全内容
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