CD4023资料

CD4023BC Buffered Triple 3-Input NAND GateOctober 1987Revised August 2000

CD4023BC

Buffered Triple 3-Input NAND Gate

General Description

These triple gates are monolithic complementary MOS(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equalsource and sink current capabilities and conform to stan-dard B series output drive. The devices also have bufferedoutputs which improve transfer characteristics by providingvery high gain. All inputs are protected against static dis-charge with diodes to VDD and VSS.

Features

sWide supply voltage range: 3.0V to 15VsHigh noise immunity:0.45 VDD (typ)sLow power TTL compatibility:

fan out of 2 driving 74L or 1 driving 74LSs5V–10V–15V parametric ratingssSymmetrical output characteristics

sMaximum input leakage 1 µA at 15V over full temperature range

Ordering Code:

Order NumberCD4023BCMCD4023BCSCD4023BCN

Package Number

M14AM14DN14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.

Connection DiagramBlock Diagram

1

/3 Device Shown

Top View

*All Inputs Protected by Standard CMOS Input Protection Circuit.

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CD4023BCAbsolute Maximum Ratings(Note 1)

(Note 2)

DC Supply Voltage (VDD)Input Voltage (VIN)Storage Temp. Range (TS)Power Dissipation (PD)Dual-In-LineSmall OutlineLead Temperature (TL)(Soldering, 10 seconds)

260°C700 mW500 mW

Recommended OperatingConditions

DC Supply Voltage (VDD)Input Voltage (VIN)

Operating Temperature Range (TA)

5VDC to 15 VDC0VDC to VDD VDC

−0.5VDCto+18VDC−0.5VDCtoVDD+0.5VDC

−65°C to +150°C

−40°C to +85°C

Note 1: “Absolute Maximum Ratings” are those values beyond which thesafety of the device cannot be guaranteed; they are not meant to imply thatthe devices should be operated at these limits. The table of “Recom-mended Operating Conditions” and “Electrical Characteristics” providesconditions for actual device operation.Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

SymbolIDD

Parameter

Quiescent Device Current

VDD = 5VVDD = 10VVDD = 15V

VOL

LOW Level Output VoltageVDD = 5V

VDD = 10VVDD = 15V

VOH

HIGH Level Output VoltageVDD = 5V

VDD = 10VVDD = 15V

VIL

LOW Level Input Voltage

VDD=5V, VO=4.5VVDD=10V, VO=9.0VVDD=15V, VO=13.5V

VIH

HIGH Level Input Voltage

VDD=5V, VO=0.5VVDD=10V, VO=1.0VVDD=15V, VO=1.5V

IOL

LOW Level Output CurrentVDD=5V, VO = 0.4V(Note 4)

IOH

VDD = 10V, VO = 0.5VVDD = 15V, VO = 1.5V

HIGH Level Output CurrentVDD = 5V, VO = 4.6V(Note 4)

IIN

Input Current

VDD = 10V, VO = 9.5VVDD = 15V, VO = 13.5VVDD = 15V, VIN = 0VVDD = 15V, VIN = 15V

Note 3: VSS = 0V unless otherwise specified.Note 4: IOH and IOL are tested one output at a time.

Conditions

−40°CMin

Typ1.02.04.00.050.050.05

4.959.9514.95

1.5

|IO|<1µA

3.5

|IO|<1µA

7.011.00.521.33.6−0.52−1.3−3.6

−0.30.33.04.0

7.011.00.441.13.0−0.44−1.1−3.04.959.9514.95Min

+25°CTyp0.0040.0050.00600051015246690.882.28−0.88−2.2−8−10−510−5

−0.30.31.53.04.0Max1.02.04.00.050.050.05

+85°CMin

Max7.515300.050.050.05

4.959.9514.95

1.53.04.0

7.0

Units

µA

V

V

V

3.5 33.5

11.00.360.902.4−0.36−0.90−2.4

−1.01.0

V

mA

mA

µA

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CD4023BCAC Electrical Characteristics (Note 5)

TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise specifiedSymboltPHL

Parameter

Propagation Delay, HIGH-to-LOW Level

ConditionsVDD = 5VVDD = 10VVDD = 15V

tPLH

Propagation Delay, LOW-to-HIGH Level

VDD = 5VVDD = 10VVDD = 15V

tTHL,tTLHCINCPD

Average Input CapacitancePower Dissipation Capacity (Note 6)Transition Time

VDD = 5VVDD = 10VVDD = 15VAny InputAny Gate

Min

Typ13060401105035905040517

Max2501007025010070200100807.5

pFpFnsnsnsUnits

Note 5: AC Parameters are guaranteed by DC correlated testing.

Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note AN-90.

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CD4023BCPhysical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

Package Number M14A

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CD4023BCPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

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CD4023BC Buffered Triple 3-Input NAND GatePhysical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.www.fairchildsemi.com

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2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or effectiveness.

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