LEARNING THE RELATIONSHIP BETWEEN COMPUTER ARCHITECTURE AND TECHNOLOGY BY RECONFIGURING

BY RECONFIGURING

Domingo Benitez *

Abstract

This paper proposes an approach for teaching ComputerOrganization and Architecture which is based on buildingknowledge from the bottom up. Students should design threeprocessors with increased complexity and measure theirperformanc*es. These processor designs are assigned during asequence of three 15-week courses and are implemented using alow-cost FPGA-based reconfigurable platform developed atUniversity of Las Palmas G.C. Emphasis is placed on comparingthe relation of computer performance with hardware requirementsto what has been experimented during the recent history ofcomputers. Our experience shows that students understand betterthe architecture-technology relation and gain a sense ofaccomplishment on the computer design when given theopportunity to use real hardware. It is demonstrated here that thelearning curve can be modelled as an exponential function of time.

I. INTRODUCTION

Learning by doing is a teaching methodology that is used atmany universities ([4], [3]). Rapid prototyping has been ap-plied in this methodology since the equipments required areavailable to schools at prices comparable to existing instruc-tional laboratories. We try to teach the relationship betweencomputer architecture and technology by using FPGA devi-ces. Our approach is based on the following two experi-mental rules.

Rule 1: Microprocessor performance has grown at an annualrate about % [7]. Modeling the variation of computer per-formance with time, it can be expressed as:

P(t) = 0,65 e0,43 t

(1)

where P is performance, t is time measured in years, and wesuppose that P(1)=1.

Rule 2: Moore’s law says that the number of transistors on aprocessor doubles approximately every 18 months [9]. Thisis equivalent to say that the number of transistors grows atan annual rate about 59%. The following formula modelsthis temporal rate,

X(t) = 0,63 e0,46 t(2)where X is the number of transistors, t is time measured in

years, and we suppose that X(1)=1. * University of Las Palmas G.C. Campus Tafira. 35017 LasPalmas. Spain. E-mail: dbenitez@dis.ulpgc.esThis work was developed under projects TIC95-0230-C02-01 andTIC98-0322-C03-02

Combining the previous two laws,

P = X0,93

(3)

Expression (3) can model the average relation between pro-cessor performance and hardware complexity experimentedduring the recent history of computers. This function is amain point in our education methodology. Students experi-ment with a function similar to (3) while learning computerarchitecture concepts.

Computer Organization and Architecture education in theComputer Engineer curriculum at University of Las PalmasG.C. is divided into three semester-based courses taken insequence at the beginning of three consecutive years. Stu-dents have laboratory assignments for each of these coursesin which they design a processor with increased hardwarecomplexity and computer performance (see fig. 1). Theseprocessors are grouped into a family called CEREPRO.PP = X0,93XComputerComputerFundamentalComputerOrganizationArchitectureFigure 1: Relationship between computer performance (P)and number of transistors (X) in the recent history ofcomputers in correspondence with the sequence of

Computer Engineering courses.This paper describes in section II general characteristics ofthe family of processors and the low-cost reconfigurableboard used in their implementations. Section III describesthe sequence of undergraduate courses where processors aredesigned, and finally some conclusions are exposed in sec-tion IV.

II. CEREPRO PROJECT

CEREPRO is an acronym made up from “CEntral REducedPROcessing unit”. This is the name of an educational pro-ject based on the development of processors using program-mable devices. This processor set is grouped into a familycalled CEREPRO which is formed at this moment by sixprocessors (C0, C1, C2, C3, C4, C5). Each processor is dif-ferentiated by its instruction set architecture which can beclassified by the type of internal storage. The major choicesare an accumulator or a set of registers.

Each processor has been synthesized onto the same pro-grammable device from Altera using MAX+plus II software[1]. The results of the synthesis process are depicted in figu-re 2 supposing that the number of transistors (X) is obtainedby multiplying the number of gates by a constant factor.Computer performance (P’) is measured by running a mul-tiplying algorithm with the same input data and calculatingthe inverse of CPU time. Performing power regression cal-culations, it can be obtained the following formula for mo-deling computer performance in CEREPRO family (see fig.2):

P’ = 0, X

1,81

with the purpose of other educational boards [8]. It is usedby several courses and therefore, its cost can be consideredby restricted budgets. The cost of each board is about 400$.

Normalized performance (P')5040302010

P’ = 0, XC4C0 C2C1C51,81ExperimentalModel00,00

C35,00

10,00

Normalized number of

transistors (X)

Figure 2: Relationship between computer performance (P’)and number of transistors (X) found out in CEREPRO

processors.

III. UNDERGRADUATE COURSES FOR COMPUTER

ARCHITECTURE EDUCATIONRapid prototyping design laboratory can demonstrate andunify many of the ideas taught in numerous undergraduateclasses. This type of laboratory is ideal for students to learnthe basic processor design skills as has been shown in theliterature ([3], [8]). We use this type of laboratory for stu-dents to put into practice computer architecture concepts.A sequence of three 15-week courses on Computer Archi-tecture are required in the Computer Engineer curriculum:Computer Fundamentals, Computer Organization, and Com-puter Architecture. These courses use a main book whichare [6], [7], and [5] respectively. Each course has a majorassignment in which a processor from CEREPRO family isdesigned and implemented using our reconfigurable board.

(4)

This is equivalent to say that the computer performancegrowth would increase at an annual rate of 130% if Moore’slaw is considered to be the temporal model of hardwarecomplexity.

We have developed a low-cost prototyping platform whichallows the design and implementation of all CEREPROprocessors (see fig. 3). It is constituted by a programmabledevice from Altera, two 2KB 4-port memory modules fromIDT, KB EPROM, and KB high speed SRAM. Thisboard has 3 I/O ports: 1 full-duplex serial port with pro-grammable transmission rate, 1 serial download port, and a40-bit configurable bidirectional port.

Our prototyping platform is not intended to be used only byone course on processor or computer design in comparison

Figure 3: The reconfigurable prototyping platform.

Computer Fundamentals is required 5 hours, one quarter.Students are already familiar with digital design, Field Pro-grammable Gate Arrays, and modeling and simulation ofsimple digital logic circuits from a prerequisite course ca-lled Digital Systems. Lectures are held 3 hours a week, and2 hours of laboratory work per week are required. ComputerFundamentals covers state machine design and an introduc-tion to computer organization. The final design example is avery simple computer based on C0 [2]. This is a 8-bit pro-cessor with instruction set architecture based on an accumu-lator. Students develop a schematic with simulation using amodern digital CAD tool, synthesize onto the FPGA whichis contained in the prototyping board, and develop a bench-mark program that multiplies two 8-bit numbers. Metrics forthe design include gate count and total execution time.Computer Organization is required 4 hours, one quarter.The goals of this course are: computer arithmetic, RISC-li-ke processor design, memory hierarchy, and I/O. At the endof Computer Organization, students should have a basic un-derstanding of computer operations from the high level lan-guage programming level to the gate level implementationof the computer system. This course has a major assignmentin which C1 is designed and implemented using our reconfi-gurable board. C1 is a 16-bit processor with a load-store ar-chitecture and multi-cycle data-path. Its organization is a li-ttle bit more complicated than C0’s. Students complete amachine language program which multiplies two numbers.Finally, they compare the gate count and total execution ti-me with the results obtained in the synthesis process of C0.So, the complexity of the processor design is increased asstudent experience grows (see figs. 1 and 2). VHDL langua-ge has been introduced into the laboratory work, and we ha-ve experienced that this high level language allows proces-sor prototyping to be relatively rapid.

Computer Architecture requires 2 hours of lecture and 2hours of laboratory work per week. This course focuses onadvanced uniprocessors, including microarchitecture andinstruction level parallelism. A major assignment is requiredin which students develop the processor called C4 with pi-pelined datapath as described in [7] and [5]. It is the mostcomplex of CEREPRO family and implements a subset ofthe DLX machine with 13 instructions. As in earlier cour-ses, students measure gate count and execution time andcompare these results with those obtained previously.These three courses are taken in the first semester of threeconsecutive academic years at our university. So, the har-dware complexity of processor designs assigned in the res-pective laboratory work increases as:

X(t) = 0,48 e0,85 t

(5)

which is equivalent to a factor “2,34x” per year (134%/yr).On the other hand, the performance of successive proces-sors grows as

P(t) = 0,2 e

1,74 t (6)

which is equivalent to “5,7x” per year (470%/yr).

Current technology can put 2’5 millions of gates on a singlechip, and one of our teaching goals is for future computerengineers to manage this number of gates and even more.Using expression (5) and starting from a 2000 gates designin Computer Fundamentals, students could manage 2’5 mi-llions of gates designs after 9 years. This is a very long termeducational objective. Nevertheless, if the processor com-plexity in educational projects could be increased everysemester than every year, students would be able to managereal processor designs after 5 years approximately.

IV. CONCLUSIONS

Students learn computer architecture rules in theoreticalclasses and then, some of these rules are put into practice byreconfiguring real prototyping hardware. With our method,we have experienced an increase in the learning phase ofstudents that is higher than the increase in growth of com-puter performance and complexity in the recent history ofcomputers. The learning curve of computer architectureconcepts and related technology aspects may be qualitative-ly modeled as an exponential function of time. If studentsbegin a computer engineering career with no computer ar-chitecture knowledge, they can manage current processorcomplexity after approximately 5 years supposing a expo-nential complexity curve X(t) = 0,48 e0,85 t

and startingwith a 2000 gates design. This is the reason why future pro-cessors may be designed by computer engineers that are ta-king their careers now. I think this approach works becauseit builds knowledge from the bottom up and students enjoyenormously when designing computers.

V. ACKNOWLEGMENTS

The author would like to thank the students who have con-tributed to CEREPRO project: F.Peña, M.Gonzalez, P.Ra-mírez, J.J. Gutierrez, J.Jiménez and P.Suárez. Software do-nation from Altera is thankfully acknowledged.

VI. REFERENCES

[1] Altera; Data Book; Altera, 1996.[2] D. Benítez, F. J. Peña; Processor Design using Programmable Logic

Devices Oriented to Computer Technology Education; InformaciónTecnológica, Vol.9, No.9, 1998.

[3] J.O.Hamblen, H.Owen, S.Yalamanchili, B.Dao, Using rapid

prototyping in Computer Architecture Design Laboratories, 2ndAnnual Workshop on Computer Architecture Education, TCCANewsletter, June 1996, pp.44-52.

[4] J.L.Hennessy, The Computer Architecture Curriculum at Stanford:

Challenges and Approaches, 2nd Annual Workshop on ComputerArchitecture Education, TCCA Newsletter, June 1996, pp.56.

[5] J.L.Hennessy, D.Patersson; Computer Architecture. A QuantitativeApproach (second edition); Morgan Kaufmann Publishers, 1996.[6] M. Morris Mano, Charles R. Krime; Logic and Computer DesignFundamentals; Prentice-Hall International Inc., 1997.[7] D.Patersson, J.L.Hennessy; Computer Organization and Design(second edition); Morgan Kaufmann Publishers, 1998.[8] A.Varma, L.Kalampoukas, D.Stiliadis, Q.Jacobson, CPU design kit:

An instructional prototyping platform for teaching processor design,2nd Annual Workshop on Computer Architecture Education, TCCANewsletter, June 1996, pp.23-26.

[9] A. Yu; “The Future of Microprocessors”; IEEE Micro, Vol.16, No.6,

pp.46-53, 1996.